blob: 31a47347fbc801838197d60666c82c1ec3740a5c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
|
========================================================================
UHD - USRP-E1XX Series Application Notes
========================================================================
.. contents:: Table of Contents
------------------------------------------------------------------------
Specify a Non-standard Image
------------------------------------------------------------------------
UHD will automatically select the USRP-Embedded FPGA image from the
installed images package. The FPGA image selection can be overridden with the
**--fpga=** device address parameter.
Example device address string representations to specify non-standard FPGA
image:
::
fpga=usrp_e100_custom.bin
------------------------------------------------------------------------
Changing the Master Clock Rate
------------------------------------------------------------------------
The master clock rate of the USRP-Embedded feeds both the FPGA DSP and the codec
chip. Hundreds of rates between 32MHz and 64MHz are available. A few notable
rates are:
* **64MHz:** maximum rate of the codec chip
* **61.44MHz:** good for UMTS/WCDMA applications
* **52Mhz:** good for GSM applications
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Set 61.44MHz - uses external VCXO
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To use the 61.44MHz clock rate with the USRP-Embedded, two jumpers must be moved
on the device.
* **J16** is a two pin header; remove the jumper (or leave it on pin1 only).
* **J15** is a three pin header; move the jumper to (pin1, pin2).
**Note:** See instructions below to communicate the desired clock rate UHD.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Set other rates - uses internal VCO
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To use other clock rates, the jumpers will need to be in the default position.
* **J16** is a two pin header; move the jumper to (pin1, pin2).
* **J15** is a three pin header; move the jumper to (pin2, pin3).
To communicate the desired clock rate into UHD,
specify the a special device address argument,
where the key is **master_clock_rate** and the value is a rate in Hz.
Example:
::
uhd_usrp_probe --args="master_clock_rate=52e6"
------------------------------------------------------------------------
Clock Synchronization
------------------------------------------------------------------------
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Ref Clock - 10MHz
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking
by selecting **REF_INT** for the **clock_config_t**.
Alternately, an external 10MHz reference clock can be supplied by soldering
a connector.
* Connector **J10** (REF_IN) needs MCX connector **WM5541-ND** or similar.
* Square wave will offer the best phase noise performance, but sinusoid is acceptable.
* **Power level:** 0 to 15dBm
* Select **REF_SMA** in **clock_config_t**.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
PPS - Pulse Per Second
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
An exteral PPS signal for timestamp synchronization can be supplied by soldering
a connector.
* Connector **J13** (PPS) needs MCX connector **WM5541-ND** or similar.
* Requires a square wave signal.
* **Amplitude:** 3.3 to 5Vpp
Test the PPS input with the following app:
* **<args** are device address arguments (optional if only one USRP is on your machine).
::
cd <install-path>/share/uhd/examples
./test_pps_input --args=<args>
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Internal GPSDO
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Please see the `Internal GPSDO Application Notes <./gpsdo.html>`_
for information on configuring and using the internal GPSDO.
UHD will always try to detect an installed GPSDO at runtime.
There is not a special EEPROM value to burn for GPSDO detection.
------------------------------------------------------------------------
Hardware Setup Notes
------------------------------------------------------------------------
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Front panel LEDs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The LEDs on the front panel can be useful in debugging hardware and software
issues. The LEDs reveal the following about the state of the device:
* **LED A:** transmitting
* **LED B:** fpga loaded
* **LED C:** receiving
* **LED D:** fpga loaded
* **LED E:** reference lock
* **LED F:** board power
------------------------------------------------------------------------
Miscellaneous
------------------------------------------------------------------------
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Available Sensors
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The following sensors are available;
they can be queried through the API.
* **ref_locked:** clock reference locked (internal/external)
* other sensors are added when the GPSDO is enabled
|
