1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
|
#Generated by MIG Version 1.8
#Coregen 14.4 - Build Number P.49d on Thu Jan 17 10:44:37 2013
#FPGA Part xc7k410t-ffg900-2
IO Bank,Pin Number,Signal Name,IO Standard,Direction,Slew Rate,DiffPair Type,DiffPair Signal
34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
32,AD17,sys_clk_i,LVCMOS18,IN,,,
34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
34,AJ4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
34,AH6,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
34,AH5,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
34,AH2,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
34,AH4,ddr3_dm[2],SSTL15,OUT,FAST,,
34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
32,AD17,sys_clk_i,LVCMOS18,IN,,,
34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]
|
