blob: a55fc12987d29115bbbf4020485f39c216461072 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
#
# Copyright 2017 Ettus Research, A National Instruments Company
# SPDX-License-Identifier: LGPL-3.0
#
# No need for any asynchronous clock groups between bus_clk and the recovered clocks,
# because bus_clk already has a blanket asynchronous constraint from the top level XDC.
# Remove analysis between the xge_clk and the recovered clocks from the MGT PHYs,
# since they cannot be related to one another with any known phase or period.
set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk]
set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk]
set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk]
set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk]
set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}]
set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}]
set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}]
set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}]
|
