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path: root/fpga/usrp3/lib/vita_200/build_16_to_12
blob: 45e354e9e484a3f68422211356d52c2c99809ad9 (plain)
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iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_16sc_to_12sc_tb.v -o chdr_16sc_to_12sc_tb