build_12_to_16 « vita « lib « usrp3 « fpga - uhd - Ettus' UHD Repository

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path: root/fpga/usrp3/lib/vita/build_12_to_16

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1	`iverilog -y . -y ../dsp/ -y ../control/ -Wall chdr_12sc_to_16sc_tb.v -o chdr_12sc_to_16sc_tb`