blob: 3fda278f85bf51892cd7eb8a34e2106062e9b4da (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
|
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../packet_proc/eth_dispatch_tb.v
vlogcomp -work work ../../packet_proc/eth_dispatch.v
vlogcomp -work work ../../fifo/axi_fifo_short.v
vlogcomp -work work ../../fifo/axi_fifo.v
vlogcomp -work work ../../control/ram_2port.v
vlogcomp -work work ../../control/setting_reg.v
vlogcomp -work work ../../sim/axi_probe_tb.v
fuse work.eth_dispatch_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o eth_dispatch_tb.exe
# run the simulation scrip
./eth_dispatch_tb.exe -gui #-tclbatch simcmds.tcl
|
