addsub_hls.tcl « addsub_hls « hls « lib « usrp3 « fpga - uhd - Ettus' UHD Repository

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path: root/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl

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1 2	`# Set target clock rate to 200 MHz create_clock -period 5 -name default`