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//
// Copyright 2014 Ettus Research LLC
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
module add2_and_clip
#(parameter WIDTH=16)
(input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output [WIDTH-1:0] sum);
wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
(.in(sum_int),.out(sum));
endmodule // add2_and_clip
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