fpga/usrp2/gpmc/edge_sync.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

module edge_sync
  #(parameter POSEDGE = 1)
   (input clk,
    input rst,
    input sig,
    output trig);
   
   reg [1:0] delay;
   
   always @(posedge clk)
     if(rst)
       delay <= 2'b00;
     else
       delay <= {delay[0],sig};
   
   assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10);
   
endmodule // edge_sync