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path: root/fpga/usrp2/extramfifo/ext_fifo_tb.prj
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verilog work "./ext_fifo_tb.v"
verilog work "./ext_fifo.v"
verilog work "./nobl_fifo.v"
verilog work "./nobl_if.v"
verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v"
verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v"
verilog work "../models/CY7C1356C/cy1356.v"
verilog work "../models/idt71v65603s150.v"
verilog work "$XILINX/verilog/src/glbl.v"