fpga/usrp1/megacells/fifo_1kx16_inst.v


1
2
3
4
5
6
7
8
9
10
11
12

fifo_1kx16	fifo_1kx16_inst (
	.aclr ( aclr_sig ),
	.clock ( clock_sig ),
	.data ( data_sig ),
	.rdreq ( rdreq_sig ),
	.wrreq ( wrreq_sig ),
	.almost_empty ( almost_empty_sig ),
	.empty ( empty_sig ),
	.full ( full_sig ),
	.q ( q_sig ),
	.usedw ( usedw_sig )
	);