1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
/*
* USRP - Universal Software Radio Peripheral
*
* Copyright (C) 2003,2004 Free Software Foundation, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
*/
#ifndef _USRP_COMMANDS_H_
#define _USRP_COMMANDS_H_
#include <usrp_interfaces.h>
#include <usrp_spi_defs.h>
#define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2
// ----------------------------------------------------------------
// Vendor bmRequestType's
// ----------------------------------------------------------------
#define VRT_VENDOR_IN 0xC0
#define VRT_VENDOR_OUT 0x40
// ----------------------------------------------------------------
// USRP Vendor Requests
//
// Note that Cypress reserves [0xA0,0xAF].
// 0xA0 is the firmware load function.
// ----------------------------------------------------------------
// IN commands
#define VRQ_GET_STATUS 0x80
#define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
#define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
#define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read
#define VRQ_SPI_READ 0x82 // wValue: optional header bytes
// wIndexH: enables
// wIndexL: format
// len: how much to read
#define VRQ_FW_COMPAT 0x83 //low 16 bits
// OUT commands
#define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
#define VRQ_FPGA_LOAD 0x02
# define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble.
# define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data
# define FL_END 2 // wIndexL: end programming cycle, check for success.
// stalls endpoint if trouble.
#define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first
#define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1}
#define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1}
#define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1}
// see below VRQ_FPGA_SET_{TX,RX}_RESET
#define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits
# define SLEEP_ADC0 0x01
# define SLEEP_ADC1 0x02
# define SLEEP_DAC0 0x04
# define SLEEP_DAC1 0x08
#define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data
#define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes
// wIndexH: enables
// wIndexL: format
// len: how much to write
#define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
#define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
#define VRQ_RESET_GPIF 0x0c
#define VRQ_ENABLE_GPIF 0x0d
#define VRQ_CLEAR_FPGA_FIFO 0x0e
// -------------------------------------------------------------------
// we store the hashes at fixed addresses in the FX2 internal memory
#define USRP_HASH_SLOT_0_ADDR 0xe1e0
#define USRP_HASH_SLOT_1_ADDR 0xe1f0
#endif /* _USRP_COMMANDS_H_ */
|
