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| * | | | | | | | | | | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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| * | | | | | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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| * | | | | | | | | | | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-274-172/+72
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
| * \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | | | | | | | | | test full width packetsMatt Ettus2010-05-241-0/+27
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| * | | | | | | | | | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
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| * | | | | | | | | | | | | fix double declarationMatt Ettus2010-05-211-1/+0
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| * | | | | | | | | | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
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| * | | | | | | | | | | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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| * | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| | * | | | | | | | | | | | | better debug pinsMatt Ettus2010-05-171-6/+4
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| * | | | | | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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| * | | | | | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-126-66/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packet gen and test
| * | | | | | | | | | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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| * | | | | | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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| * | | | | | | | | | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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| * | | | | | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-108-561/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | safe_u1e necessary.
| * | | | | | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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| * | | | | | | | | | | | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
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| * | | | | | | | | | | | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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| * | | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| | * | | | | | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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| * | | | | | | | | | | | | | | changed commentMatt Ettus2010-05-041-1/+1
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| * | | | | | | | | | | | | | have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO
| * | | | | | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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| * | | | | | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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| * | | | | | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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| * | | | | | | | | | | | | | Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
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| * | | | | | | | | | | | | | Register outputs to omap to prevent runt pulses from falsely triggering ↵Matt Ettus2010-04-233-7/+20
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| * | | | | | | | | | | | | | find time_64bitMatt Ettus2010-04-201-0/+1
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| * | | | | | | | | | | | | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
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| * | | | | | | | | | | | | | access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
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| * | | | | | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-155-37/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for gpmc
| * | | | | | | | | | | | | | async gpmc progressMatt Ettus2010-04-154-18/+173
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| * | | | | | | | | | | | | | change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
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| * | | | | | | | | | | | | | add bus error reportingMatt Ettus2010-04-151-3/+9
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| * | | | | | | | | | | | | | correct name of moduleMatt Ettus2010-04-151-2/+2
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| * | | | | | | | | | | | | | progress on synchronous gpmc, but it may not be possible due to the limited ↵Matt Ettus2010-04-153-43/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | number of clock edges
| * | | | | | | | | | | | | | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-153-3/+100
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| * | | | | | | | | | | | | | handle all tri-state in the top level of gpmcMatt Ettus2010-04-153-6/+8
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| * | | | | | | | | | | | | | more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
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| * | | | | | | | | | | | | | more progress on synchronous interfaceMatt Ettus2010-04-144-26/+95
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| * | | | | | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
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| * | | | | | | | | | | | | | make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
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| * | | | | | | | | | | | | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
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| * | | | | | | | | | | | | | probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
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| * | | | | | | | | | | | | | minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
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| * | | | | | | | | | | | | | lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
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| * | | | | | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
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| * | | | | | | | | | | | | | split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
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