aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2
Commit message (Collapse)AuthorAgeFilesLines
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
|
* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
|
* added in a loopback fifoMatt Ettus2010-04-141-4/+11
|
* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
|
* minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
|
* lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
|
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
|
* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
|
* added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
| | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
|
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
|
* remove timescale junkMatt Ettus2010-03-265-21/+19
| | | | | | | | get rid of asynchronous resets fix spelling error corrected comment
* connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | be read/controlled from SW
* Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
|\
| * Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
| |\
| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
| | |
| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
| | |
| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
| | | | | | | | | | | | workaround
| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
| | |
| * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
| | |
| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
| | |
| * | copied over from quad radioMatt Ettus2010-02-081-0/+60
| | |
| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
| | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| * | just debug pin changesMatt Ettus2010-01-252-1/+12
| | |
| * | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
| | |
| * | moved into subdirJosh Blum2010-01-22653-0/+1558662
| /
* | connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
* | debug pinsMatt Ettus2010-02-251-2/+3
| |
* | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
| |
* | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
| |
* | gpmc debug pinsMatt Ettus2010-02-252-4/+14
| |
* | point to the new filesMatt Ettus2010-02-251-0/+2
| |
* | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
| |
* | loopback and testMatt Ettus2010-02-252-7/+38
| |
* | corrected logicMatt Ettus2010-02-251-17/+7
| |
* | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
| |
* | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
| |
* | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
| |
* | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
| |
* | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
|\| | | | | | | | | Conflicts: .gitignore
| * proper initialization of the ramMatt Ettus2010-02-231-1/+1
| |
* | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-233-6/+63
| | | | | | | | ISE chokes on the unequal size ram
* | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
| |
* | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
| |
* | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
| |
* | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
| |
* | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
| |
* | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
| |
* | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
| |
* | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
| |
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 04:42:09 +0000