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path: root/usrp2/vrt/vita_tx_control.v
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* added copyrightsJosh Blum2011-06-071-0/+17
* clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-161-1/+1
* run should actually turn on now any time in the IBS_RUN stateMatt Ettus2010-12-291-11/+8
* should keep cordic spinning and the rest of the tx going throughMatt Ettus2010-12-281-4/+33
* should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-181-4/+7
* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-131-3/+2
* reset properlyMatt Ettus2010-11-111-0/+1
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-7/+2
* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
* checkpoint in flow control packet generationMatt Ettus2010-11-111-2/+8
* provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
* attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
* implemented "next packet" and "next burst" policiesMatt Ettus2010-07-281-18/+43
* more informative error codesMatt Ettus2010-07-281-4/+6
* cleaner error handlingMatt Ettus2010-07-281-27/+28
* introduce new error typesMatt Ettus2010-07-281-15/+42
* Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-251-2/+5
* moved into subdirJosh Blum2010-01-221-0/+95
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