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* b100/e100: bump compat for inversion fix on masterJosh Blum2012-10-051-1/+1
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* e1x0: fix RX ADC I and Q inversionJosh Blum2012-10-051-1/+10
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* Merge branch 'maint'Josh Blum2012-10-051-4/+4
|\ | | | | | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v usrp2/top/E1x0/E1x0.v usrp2/top/E1x0/u1e_core.v
| * b100/e100: bump compat minor for inversion fixJosh Blum2012-10-052-2/+2
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| * e1x0: fix RX ADC I and Q inversionJosh Blum2012-10-051-2/+13
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| * b100: fix RX ADC I and Q inversionJosh Blum2012-10-051-4/+4
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* | b100: fpga makefile for 2rx no txJosh Blum2012-09-014-1/+134
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* | e100: tighten timing - less routing on EM_AJosh Blum2012-07-192-2/+2
| | | | | | | | | | There were a few places it was ok to use addr over EM_A. This makes routing sligtly easier for GPMC signals.
* | u1plus: added sr misc hook for clock syncJosh Blum2012-07-181-1/+8
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* | e100: renamed top level for E100/E110 to E1x0Josh Blum2012-07-175-9/+9
| | | | | | | | Some minor tweaks to gpmc_to_fifo + timing
* | E100: squash E100/E110 top level workJosh Blum2012-07-166-531/+84
| | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPMC. Uses the common core for E100/B100.
* | gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-161-15/+11
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* | Merge branch 'master' into nextJosh Blum2012-07-161-1/+1
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| * | Merge branch 'maint'Josh Blum2012-07-161-1/+1
| |\| | | | | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| | * e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-151-1/+1
| | | | | | | | | | | | This effectivly works around bus initial transaction issues.
* | | B100: squash B100 top level workJosh Blum2012-07-024-406/+348
|/ / | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPIF. Implements a common core for E100/B100.
* | b100: removed unused proto filesJosh Blum2012-06-133-390/+0
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* | Merge branch 'maint'Josh Blum2012-05-101-1/+1
|\| | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| * e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
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* | e100/b100: bumped compat number for timed commands mergeJosh Blum2012-04-252-2/+2
| | | | | | | | | | There were common FPGA changes and an incompatibility. This should have been done before the merge anyhow.
* | b100: implement packet-end/flush cycle timeoutJosh Blum2012-04-241-1/+1
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* | N2x0: updated the bootloader w/ latest from fwJosh Blum2012-04-201-390/+390
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* | usrp2: remove settings_fifo_ctrl, meets timingJosh Blum2012-04-201-2/+11
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* | usrp: work on meeting timing constraintsJosh Blum2012-04-102-16/+16
| | | | | | | | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage
* | Merge branch 'master' into nextJosh Blum2012-04-093-2/+62
|\ \ | | | | | | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
| * | Merge branch 'maint'Josh Blum2012-04-094-5/+5
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| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-094-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
| * | Merge branch 'maint'Josh Blum2012-04-021-1/+1
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| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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* | Merge branch 'master' into nextJosh Blum2012-03-261-1/+1
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| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-241-1/+1
| | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-162-2/+2
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* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-162-28/+28
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* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-163-3/+3
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* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-163-320/+320
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* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
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* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-163-351/+394
| | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* | spi: created simple spi core (sr based)Josh Blum2012-03-162-383/+397
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* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-162-2/+2
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* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-161-5/+10
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* | srb: created command queue, in and out state machinesJosh Blum2012-03-162-4/+2
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* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-161-4/+38
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* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
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* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-064-4/+4
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* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-044-62/+51
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* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
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