Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 1 | -6/+14 | |
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* | | | async seems to work with packet lengths now. Still need to do wishbone regs ↵ | Matt Ettus | 2010-04-15 | 1 | -3/+3 | |
| | | | | | | | | | | | | for gpmc | |||||
* | | | async gpmc progress | Matt Ettus | 2010-04-15 | 2 | -18/+20 | |
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* | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 1 | -1/+1 | |
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* | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 1 | -0/+2 | |
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* | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 1 | -0/+1 | |
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* | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 1 | -1/+1 | |
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* | | | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 | |
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* | | | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 1 | -0/+3 | |
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* | | | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 1 | -39/+7 | |
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* | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 2 | -33/+44 | |
| | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | |||||
* | | | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 | |
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* | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵ | Matt Ettus | 2010-03-26 | 3 | -8/+26 | |
| | | | | | | | | | | | | be read/controlled from SW | |||||
* | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 2 | -57/+179 | |
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| * | | moved fifos around, now easier to see where they are and how big | Matt Ettus | 2010-03-25 | 1 | -10/+23 | |
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| * | | bigger fifo on UDP TX path, to possibly fix overruns on decim=4 | Matt Ettus | 2010-03-24 | 1 | -2/+11 | |
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| * | | pps and vita time debug pins | Matt Ettus | 2010-03-23 | 1 | -3/+6 | |
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| * | | more debug for fixing E's | Matt Ettus | 2010-03-10 | 1 | -5/+12 | |
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| * | | better debug pins for going after cascading E's | Matt Ettus | 2010-03-10 | 1 | -1/+5 | |
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| * | | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 2 | -27/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v | |||||
| * | | just debug pin changes | Matt Ettus | 2010-01-25 | 1 | -1/+5 | |
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| * | | moved into subdir | Josh Blum | 2010-01-22 | 41 | -0/+8358 | |
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* | | connected spi pins, but the spi core still needs to be redone for 16 bit ↵ | Matt Ettus | 2010-03-25 | 3 | -40/+60 | |
| | | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs | |||||
* | | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 | |
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* | | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 | |
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* | | gpmc debug pins | Matt Ettus | 2010-02-25 | 1 | -3/+6 | |
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* | | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 | |
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* | | loopback and test | Matt Ettus | 2010-02-25 | 1 | -2/+32 | |
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* | | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 3 | -10/+24 | |
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* | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+1 | |
| | | | | | | | | ISE chokes on the unequal size ram | |||||
* | | use our fancy new debug ports | Matt Ettus | 2010-02-23 | 1 | -0/+3 | |
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* | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 2 | -3/+14 | |
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* | | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 4 | -37/+54 | |
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* | | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 2 | -11/+14 | |
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* | | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 3 | -48/+187 | |
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* | | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵ | Matt Ettus | 2010-02-18 | 2 | -4/+7 | |
| | | | | | | | | global set and reset module. | |||||
* | | wishbone bridge now with minimal functionality. Need to check | Matt Ettus | 2010-02-16 | 6 | -9/+49 | |
| | | | | | | | | timing and handle wait states. | |||||
* | | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 5 | -34/+93 | |
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* | | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 4 | -0/+553 | |
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* | | block ram interface to GPMC | Matt Ettus | 2010-02-16 | 1 | -2/+6 | |
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* | | basic read support for the GPMC, responds with 16'hBEEF | Matt Ettus | 2010-02-16 | 1 | -2/+8 | |
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* | | reorg pin defs | Matt Ettus | 2010-02-14 | 1 | -94/+102 | |
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* | | connect GPMC pins to debug bus | Matt Ettus | 2010-02-14 | 2 | -76/+94 | |
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* | | organized the pins in the ucf by function | Matt Ettus | 2010-02-09 | 1 | -56/+72 | |
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* | | builds a successful led blinker | Matt Ettus | 2010-02-09 | 3 | -2/+4 | |
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* | | first cut at blinking leds | Matt Ettus | 2010-02-09 | 4 | -345/+237 | |
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* | | skeletons that don't work yet | Matt Ettus | 2010-02-09 | 2 | -0/+607 | |
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* | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 41 | -0/+8275 | |