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* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-115-142/+201
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1019-0/+1381
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| * invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
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| * duhMatt Ettus2010-11-041-1/+1
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| * better debug pinsMatt Ettus2010-09-232-7/+11
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| * watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
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| * fix timing issue on DAC outputs with rev 2. This puts the whole system on a ↵Matt Ettus2010-09-212-50/+25
| | | | | | | | 90 degree phase shift
| * send all gpmc signals to mictorMatt Ettus2010-09-164-0/+201
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| * updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
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| * pins are different on rev2Matt Ettus2010-09-091-264/+4
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| * fixed makefile to compile with our new systemMatt Ettus2010-09-071-44/+36
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| * add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
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| * move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
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| * Merge branch 'tx_policy' into u1eMatt Ettus2010-08-252-7/+10
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * tx_policy: (21 commits) clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future rx error context packets should not be marked as errors in the fifo added compat number to usrp2 readback mux makefile dependency fix for second expansion provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host ... Conflicts: usrp2/top/u2_rev3/u2_core_udp.v
| * | no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
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| * | match the signal names in this designMatt Ettus2010-08-231-3/+3
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| * | debug pins cleanupMatt Ettus2010-08-231-3/+3
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| * | properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
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| * | catch up with tx_policyMatt Ettus2010-08-192-30/+28
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| * | attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
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| * | connect atrMatt Ettus2010-08-171-1/+1
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| * | delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
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| * | this is necessary for some reasonMatt Ettus2010-08-131-1/+2
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| * | connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
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| * | enlarge loopback fifoMatt Ettus2010-08-101-4/+1
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| * | Merge branch 'ise12' into u1eMatt Ettus2010-07-192-37/+36
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
| * | | make loopback compileMatt Ettus2010-07-141-0/+3
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| * | | Merge branch 'master' into u1eMatt Ettus2010-06-181-1/+2
| |\ \ \ | | | | | | | | | | | | | | | | | | | | * master: proper dependency tracking for the makefile
| * | | | added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
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| * | | | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-148-707/+216
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
| * | | | | debug pinsMatt Ettus2010-06-101-3/+6
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| * | | | | much bigger fifosMatt Ettus2010-06-101-2/+2
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| * | | | | proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
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| * | | | | ignoresMatt Ettus2010-06-081-0/+1
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| * | | | | debug pinsMatt Ettus2010-06-081-1/+2
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| * | | | | Merge branch 'master' into u1eMatt Ettus2010-06-082-2/+2
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: allow other clock rates in vita time report ise version in build proper name for directory name build directory with ISE version name
| * | | | | | remove double declarationMatt Ettus2010-06-061-1/+1
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| * | | | | | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
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| * | | | | | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
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| * | | | | | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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| * | | | | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-014-160/+1218
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * | | | | | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
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| | * | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-282-30/+28
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | | * | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-261-15/+14
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| | * | | | | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-284-15/+20
| | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | | * | | | | | | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | | * | | | | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-2/+3
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| | | * | | | | | removes the icache and pipelines the readsMatt Ettus2010-05-202-5/+6
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| * | | | | | | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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| * | | | | | | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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