Merge branch 'u1e' into merge_u1e

* u1e: (130 commits)
  invert led signals because they are active low
  duh
  allow for CS to rise before, at the same time, or after OE
  better debug pins
  watch the ethernet chip select on our debug bus
  fix timing issue on DAC outputs with rev 2.  This puts the whole system on a 90 degree phase shift
  send all gpmc signals to mictor
  updated pins to match rev2, removed dip switch, etc.  seems to compile ok.
  pins are different on rev2
  fixed makefile to compile with our new system
  add register to tell host about compatibility level and which image we are using
  move declaration to make loopback compile
  no need for protocol headers since we're not doing ethernet
  match the signal names in this design
  debug pins cleanup
  properly integrate the new tx chain
  catch up with tx_policy
  attach run_tx and run_rx to leds
  connect atr
  delay the q channel to make the channels line up on the AD9862
  ...

Conflicts:
	usrp2/control_lib/Makefile.srcs

19 files changed, 1381 insertions, 0 deletions

diff --git a/usrp2/top/.gitignore b/usrp2/top/.gitignore
index bf1b77066..0d90f1698 100644
--- a/usrp2/top/.gitignore
+++ b/usrp2/top/.gitignore
@@ -1 +1,2 @@
 /*.sav
+build*
diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/usrp2/top/u1e/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
new file mode 100644
index 000000000..3cb9fd8f3
--- /dev/null
+++ b/usrp2/top/u1e/Makefile
@@ -0,0 +1,101 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..291c723b8
--- /dev/null
+++ b/usrp2/top/u1e/cmdfile
@@ -0,0 +1,20 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+
diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..5fc8134fb
--- /dev/null
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ps / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+   
+   wire [2:0] debug_led;
+   wire [31:0] debug;
+   wire [1:0] debug_clk;
+
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
+   // GPMC
+   wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+   wire [15:0] EM_D;
+   wire [10:1] EM_A;
+   wire [1:0]  EM_NBE;
+   
+   reg  clk_fpga = 0, rst_fpga = 1;
+   always #15625 clk_fpga = ~clk_fpga;
+
+   initial #200000
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
+   
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model_async gpmc_model_async
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+   
+endmodule // tb_u1e
diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/u1e/timing.ucf
new file mode 100644
index 000000000..8df28c9d3
--- /dev/null
+++ b/usrp2/top/u1e/timing.ucf
@@ -0,0 +1,13 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+
+
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
new file mode 100644
index 000000000..0c487a601
--- /dev/null
+++ b/usrp2/top/u1e/u1e.ucf
@@ -0,0 +1,259 @@
+
+NET "CLK_FPGA_P"  LOC = "Y11"  ;
+NET "CLK_FPGA_N"  LOC = "Y10"  ;
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+NET "EM_NBE<1>"  LOC = "D14"  ;
+NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+#NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+
+## Overo GPIO
+NET "overo_gpio0"  LOC = "F9"  ;  # MISC GPIO for debug
+NET "overo_gpio14"  LOC = "C4"  ;  # MISC GPIO for debug
+NET "overo_gpio21"  LOC = "D5"  ;  # MISC GPIO for debug
+NET "overo_gpio22"  LOC = "A3"  ;  # MISC GPIO for debug
+NET "overo_gpio23"  LOC = "B3"  ;  # MISC GPIO for debug
+NET "overo_gpio64"  LOC = "A4"  ;  # MISC GPIO for debug
+NET "overo_gpio65"  LOC = "F8"  ;  # MISC GPIO for debug
+
+NET "overo_gpio127"  LOC = "C8"  ;  # Changed name to gpio10
+NET "overo_gpio128"  LOC = "G8"  ;  # Changed name to gpio186
+
+NET "overo_gpio144"  LOC = "A5"  ;  # tx_have_space
+NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun
+NET "overo_gpio146"  LOC = "A6"  ;  # rx_have_data
+NET "overo_gpio147"  LOC = "B6"  ;  # rx_overrun
+NET "overo_gpio163"  LOC = "D7"  ;  # MISC GPIO for debug
+NET "overo_gpio170"  LOC = "E8"  ;  # MISC GPIO for debug
+NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
+
+## Overo UART
+#NET "overo_txd1"  LOC = "C6"  ;
+#NET "overo_rxd1"  LOC = "D6"  ;
+
+## FTDI UART to USB converter
+NET "FPGA_TXD"  LOC = "G19"  ;
+NET "FPGA_RXD"  LOC = "F20"  ;
+
+#NET "SYSEN"  LOC = "C11"  ;
+
+## I2C
+NET "db_scl"  LOC = "F19"  ;
+NET "db_sda"  LOC = "F18"  ;
+
+## SPI
+### DBoard SPI
+NET "db_sclk_rx"  LOC = "D21"  ;
+NET "db_miso_rx"  LOC = "D22"  ;
+NET "db_mosi_rx"  LOC = "D20"  ;
+NET "db_sen_rx"  LOC = "E19"  ;
+NET "db_sclk_tx"  LOC = "F21"  ;
+NET "db_miso_tx"  LOC = "E20"  ;
+NET "db_mosi_tx"  LOC = "G17"  ;
+NET "db_sen_tx"  LOC = "G18"  ;
+
+### AD9862 SPI and aux SPI Interfaces
+#NET "aux_sdi_codec"  LOC = "G3"  ;
+#NET "aux_sdo_codec"  LOC = "F3"  ;
+#NET "aux_sclk_codec"  LOC = "C1"  ;
+NET "sen_codec"  LOC = "F5"  |IOSTANDARD = LVCMOS33;
+NET "mosi_codec"  LOC = "F4"  |IOSTANDARD = LVCMOS33;
+NET "miso_codec"  LOC = "H4"  ;
+NET "sclk_codec"  LOC = "H3"  |IOSTANDARD = LVCMOS33;
+
+### Clock Gen SPI
+NET "cgen_miso"  LOC = "F22"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+
+## Clock gen control
+NET "cgen_st_status"  LOC = "P20"  ;
+NET "cgen_st_ld"  LOC = "R17"  ;
+NET "cgen_st_refmon"  LOC = "P17"  ;
+NET "cgen_sync_b"  LOC = "U18"  ;
+NET "cgen_ref_sel"  LOC = "U19"  ;
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
+
+#NET "reset_codec"  LOC = "C2"  ;
+
+NET "RXSYNC"  LOC = "F2"  ;
+NET "DB<11>"  LOC = "G6"  ;
+NET "DB<10>"  LOC = "G5"  ;
+NET "DB<9>"  LOC = "E4"  ;
+NET "DB<8>"  LOC = "E3"  ;
+NET "DB<7>"  LOC = "H6"  ;
+NET "DB<6>"  LOC = "H5"  ;
+NET "DB<5>"  LOC = "H1"  ;
+NET "DB<4>"  LOC = "G1"  ;
+NET "DB<3>"  LOC = "K5"  ;
+NET "DB<2>"  LOC = "K4"  ;
+NET "DB<1>"  LOC = "H2"  ;
+NET "DB<0>"  LOC = "L5"  ;
+
+NET "DA<11>"  LOC = "K6"  ;
+NET "DA<10>"  LOC = "K3"  ;
+NET "DA<9>"  LOC = "K2"  ;
+NET "DA<8>"  LOC = "N1"  ;
+NET "DA<7>"  LOC = "N5"  ;
+NET "DA<6>"  LOC = "N6"  ;
+NET "DA<5>"  LOC = "P2"  ;
+NET "DA<4>"  LOC = "P1"  ;
+NET "DA<3>"  LOC = "R6"  ;
+NET "DA<2>"  LOC = "P6"  ;
+NET "DA<1>"  LOC = "R1"  ;
+NET "DA<0>"  LOC = "R2"  ;
+
+NET "TX<13>"  LOC = "T6"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<12>"  LOC = "U1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<11>"  LOC = "T1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<10>"  LOC = "R5"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<9>"  LOC = "V1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<8>"  LOC = "U2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<7>"  LOC = "T4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<6>"  LOC = "R3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<5>"  LOC = "W1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<4>"  LOC = "Y1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<3>"  LOC = "V3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<2>"  LOC = "V4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<1>"  LOC = "W2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<0>"  LOC = "W3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXSYNC"  LOC = "U5"   |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXBLANK"  LOC = "U4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+
+NET "PPS_IN"  LOC = "M5"  ;
+
+NET "io_tx<0>"  LOC = "AB20"  ;
+NET "io_tx<1>"  LOC = "Y17"  ;
+NET "io_tx<2>"  LOC = "Y16"  ;
+NET "io_tx<3>"  LOC = "U16"  ;
+NET "io_tx<4>"  LOC = "V16"  ;
+NET "io_tx<5>"  LOC = "AB19"  ;
+NET "io_tx<6>"  LOC = "AA19"  ;
+NET "io_tx<7>"  LOC = "U14"  ;
+NET "io_tx<8>"  LOC = "U15"  ;
+NET "io_tx<9>"  LOC = "AB17"  ;
+NET "io_tx<10>"  LOC = "AB18"  ;
+NET "io_tx<11>"  LOC = "Y13"  ;
+NET "io_tx<12>"  LOC = "W14"  ;
+NET "io_tx<13>"  LOC = "U13"  ;
+NET "io_tx<14>"  LOC = "AA15"  ;
+NET "io_tx<15>"  LOC = "AB14"  ;
+
+NET "io_rx<0>"  LOC = "Y8"  ;
+NET "io_rx<1>"  LOC = "Y9"  ;
+NET "io_rx<2>"  LOC = "V7"  ;
+NET "io_rx<3>"  LOC = "U8"  ;
+NET "io_rx<4>"  LOC = "V10"  ;
+NET "io_rx<5>"  LOC = "U9"  ;
+NET "io_rx<6>"  LOC = "AB7"  ;
+NET "io_rx<7>"  LOC = "AA8"  ;
+NET "io_rx<8>"  LOC = "W8"  ;
+NET "io_rx<9>"  LOC = "V8"  ;
+NET "io_rx<10>"  LOC = "AB5"  ;
+NET "io_rx<11>"  LOC = "AB6"  ;
+NET "io_rx<12>"  LOC = "AB4"  ;
+NET "io_rx<13>"  LOC = "AA4"  ;
+NET "io_rx<14>"  LOC = "W5"  ;
+NET "io_rx<15>"  LOC = "Y4"  ;
+
+#NET "CLKOUT2_CODEC"  LOC = "U12"  ;
+#NET "CLKOUT1_CODEC"  LOC = "V12"  ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
+#NET "fpga_cfg_done"  LOC = "AB21"  ;
+#NET "fpga_cfg_din"  LOC = "W17"  ;
+#NET "fpga_cfg_cclk"  LOC = "V17"  ;
+#NET "fpga_cfg_init_b"  LOC = "W15"  ;
+
+## Unused
+#NET "unnamed_net53"  LOC = "B1"  ;  # TMS
+#NET "unnamed_net52"  LOC = "B22"  ; # TDO
+#NET "unnamed_net51"  LOC = "D2"  ;  # TDI
+#NET "unnamed_net50"  LOC = "A21"  ; # TCK
+#NET "unnamed_net59"  LOC = "F7"  ;  # PUDC_B
+#NET "unnamed_net58"  LOC = "V6"  ;  # M2
+#NET "unnamed_net57"  LOC = "AA3"  ; # M1
+#NET "unnamed_net56"  LOC = "AB3"  ; # M0
+#NET "GND"  LOC = "V19"  ;  # Suspend, unused
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
new file mode 100644
index 000000000..445b14a03
--- /dev/null
+++ b/usrp2/top/u1e/u1e.v
@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e
+  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb, output FPGA_TXD, input FPGA_RXD,
+
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+
+   inout db_sda, inout db_scl, // I2C
+
+   output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx,   // DB TX SPI
+   output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx,   // DB TX SPI
+   output sclk_codec, output sen_codec, output mosi_codec, input miso_codec,   // AD9862 main SPI
+   output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso,     // Clock gen SPI
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+   
+   output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147,  // Fifo controls
+   input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22,  // Misc GPIO
+   input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO
+   input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO
+   
+   inout [15:0] io_tx, inout [15:0] io_rx,
+
+   output [13:0] TX, output TXSYNC, output TXBLANK,
+   input [11:0] DA, input [11:0] DB, input RXSYNC,
+  
+   input PPS_IN
+   );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Clocking
+   wire  clk_fpga, clk_fpga_in;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+   wire  clk_2x, dcm_rst, dcm_locked, clk_fb;
+   DCM #(.CLK_FEEDBACK ( "1X" ),
+	 .CLKDV_DIVIDE ( 2 ),
+	 .CLKFX_DIVIDE ( 2 ),
+	 .CLKFX_MULTIPLY ( 2 ),
+	 .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
+	 .CLKIN_PERIOD ( 15.625 ),
+	 .CLKOUT_PHASE_SHIFT ( "NONE" ),
+	 .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ),
+	 .DFS_FREQUENCY_MODE ( "LOW" ),
+	 .DLL_FREQUENCY_MODE ( "LOW" ),
+	 .DUTY_CYCLE_CORRECTION ( "TRUE" ),
+	 .FACTORY_JF ( 16'h8080 ),
+	 .PHASE_SHIFT ( 0 ),
+	 .STARTUP_WAIT ( "FALSE" ))
+   clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
+                .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), 
+		.CLKDV(), .CLKFX(), .CLKFX180(), 
+                .CLK2X(), .CLK2X180(), 
+                .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), 
+                .LOCKED(dcm_locked), .STATUS());
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI
+   wire  mosi, sclk, miso;
+   assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
+   assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
+   assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
+   assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0;
+   assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
+		 (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+
+   // /////////////////////////////////////////////////////////////////////////
+   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+   assign TXBLANK = 0;
+   wire [13:0] tx_i, tx_q;
+
+   reg[13:0] delay_q;
+   always @(posedge clk_fpga)
+     delay_q <= tx_q;
+   
+   genvar i;
+   generate
+      for(i=0;i<14;i=i+1)
+	begin : gen_dacout
+	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+	   ODDR2_inst (.Q(TX[i]),      // 1-bit DDR output data
+		       .C0(clk_fpga),  // 1-bit clock input
+		       .C1(~clk_fpga), // 1-bit clock input
+		       .CE(1'b1),      // 1-bit clock enable input
+		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
+		       .D1(delay_q[i]),   // 1-bit data input (associated with C1)
+		       .R(1'b0),       // 1-bit reset input
+		       .S(1'b0));      // 1-bit set input
+	end // block: gen_dacout
+      endgenerate
+   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
+		.C0(clk_fpga),  // 1-bit clock input
+		.C1(~clk_fpga), // 1-bit clock input
+		.CE(1'b1),      // 1-bit clock enable input
+		.D0(1'b0),   // 1-bit data input (associated with C0)
+		.D1(1'b1),   // 1-bit data input (associated with C1)
+		.R(1'b0),       // 1-bit reset input
+		.S(1'b0));      // 1-bit set input
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Main U1E Core
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), 
+		     .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+		     .db_sda(db_sda), .db_scl(db_scl),
+		     .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
+		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
+		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+		     .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
+		     .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+		     .io_tx(io_tx), .io_rx(io_rx),
+		     .tx_i(tx_i), .tx_q(tx_q), 
+		     .rx_i(DA), .rx_q(DB),
+		     .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176},
+				  {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22},
+				  {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}),
+		     .pps_in(PPS_IN) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Local Debug
+   // assign debug_clk = {clk_fpga, clk_2x };
+   // assign debug = { TXSYNC, TXBLANK, TX };
+   
+endmodule // u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
new file mode 100644
index 000000000..e7e798b34
--- /dev/null
+++ b/usrp2/top/u1e/u1e_core.v
@@ -0,0 +1,459 @@
+
+
+//`define LOOPBACK 1
+//`define TIMED 1
+`define DSP 1
+
+module u1e_core
+  (input clk_fpga, input rst_fpga,
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   output debug_txd, input debug_rxd,
+   
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+   
+   inout db_sda, inout db_scl,
+   output sclk, output [7:0] sen, output mosi, input miso,
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
+   output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+   inout [15:0] io_tx, inout [15:0] io_rx, 
+   output [13:0] tx_i, output [13:0] tx_q, 
+   input [11:0] rx_i, input [11:0] rx_q, 
+   
+   input [11:0] misc_gpio, input pps_in
+   );
+
+   localparam TXFIFOSIZE = 13;
+   localparam RXFIFOSIZE = 13;
+
+   localparam SR_RX_DSP = 0;     // 5 regs
+   localparam SR_CLEAR_FIFO = 6; // 1 reg
+   localparam SR_RX_CTRL = 8;    // 9 regs
+   localparam SR_TX_DSP = 17;    // 5 regs
+   localparam SR_TX_CTRL = 24;   // 2 regs
+   localparam SR_TIME64 = 28;    // 4 regs
+
+   wire [7:0]	COMPAT_NUM = 8'd2;
+   
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
+   
+   wire 	pps_int;
+   wire [63:0] 	vita_time;
+   reg [15:0] 	reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+
+   wire [31:0] 	debug_vt;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // GPMC Slave to Wishbone Master
+   localparam dw = 16;
+   localparam aw = 11;
+   localparam sw = 2;
+   
+   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
+   wire [aw-1:0] m0_adr;
+   wire [sw-1:0] m0_sel;
+   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
+
+   wire [31:0] 	 debug_gpmc;
+
+   wire [35:0] 	 tx_data, rx_data, tx_err_data;
+   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
+		 tx_err_src_rdy, tx_err_dst_rdy;
+   reg [15:0] 	 tx_frame_len;
+   wire [15:0] 	 rx_frame_len;
+   wire [7:0] 	 rate;
+
+   wire 	 bus_error;
+
+   wire 	 clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear;
+   
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear
+     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear));
+   assign clear_tx = clear_tx_int & do_clear;
+   assign clear_rx = clear_rx_int & do_clear;
+   
+   gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
+   gpmc (.arst(wb_rst),
+	 .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+	 .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
+	 .EM_NOE(EM_NOE),
+	 
+	 .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	 .bus_error(bus_error), .bus_reset(0),
+	 
+	 .wb_clk(wb_clk), .wb_rst(wb_rst),
+	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+	 .wb_ack_i(m0_ack),
+	 
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
+	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
+	 
+	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+	 .debug(debug_gpmc));
+
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+   wire 	 rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
+   
+`ifdef LOOPBACK
+   wire [7:0] 	 WHOAMI = 1;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
+      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+   assign tx_underrun = 0;
+   assign rx_overrun = 0;
+
+   wire 	 run_tx, run_rx, strobe_tx, strobe_rx;
+`endif // LOOPBACK
+
+`ifdef TIMED
+   wire [7:0] 	 WHOAMI = 2;
+   
+   // TX side
+   wire 	 tx_enable;
+   
+   fifo_pacer tx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
+      .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
+      .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
+      .underrun(tx_underrun), .overrun());
+   
+   packet_verifier32 pktver32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   // RX side
+   wire 	 rx_enable;
+
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
+
+   fifo_pacer rx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
+      .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
+      .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
+      .underrun(), .overrun(rx_overrun));
+   
+`endif //  `ifdef TIMED
+
+`ifdef DSP
+   wire [7:0] 	 WHOAMI = 0;
+   
+   wire [31:0] 	 debug_rx_dsp, vrc_debug, vrf_debug;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx1_data;
+   wire 	 run_rx;
+   wire [35:0] 	 vita_rx_data;
+   wire 	 vita_rx_src_rdy, vita_rx_dst_rdy;
+      
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(wb_clk),.rst(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(rx_overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
+      .debug_rx(vrc_debug));
+
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
+      .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .debug_rx(vrf_debug) );
+   
+   fifo36_mux #(.prio(0)) mux_err_stream
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy),
+      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+   
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [15:0] 	 tx_i_int, tx_q_int;
+   wire 	 run_tx;
+   
+   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
+		   .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) 
+   vita_tx_chain
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .dac_a(tx_i_int),.dac_b(tx_q_int),
+      .underrun(underrun), .run(run_tx),
+      .debug(debug_vt));
+   
+   assign tx_i = tx_i_int[15:2];
+   assign tx_q = tx_q_int[15:2];
+   
+`else // !`ifdef DSP
+   // Dummy DSP signal generator for test purposes
+   wire [23:0] 	 tx_i_int, tx_q_int;
+   wire [23:0] 	 freq = {reg_test,8'd0};
+   reg [23:0] 	 phase;
+   
+   always @(posedge wb_clk)
+     phase <= phase + freq;
+   
+   cordic_z24 #(.bitwidth(24)) tx_cordic
+     (.clock(wb_clk), .reset(wb_rst), .enable(1),
+      .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
+
+   assign tx_i = tx_i_int[23:10];
+   assign tx_q = tx_q_int[23:10];
+`endif // !`ifdef DSP
+      
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Intercon, single master
+   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
+		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
+		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
+		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
+   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
+   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
+   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
+   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
+   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
+   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
+   
+   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
+		.s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF),
+		.s2_addr(4'h2), .s2_mask(4'hF),	.s3_addr(4'h3), .s3_mask(4'hF),
+		.s4_addr(4'h4), .s4_mask(4'hF),	.s5_addr(4'h5), .s5_mask(4'hF),
+		.s6_addr(4'h6), .s6_mask(4'hF),	.s7_addr(4'h7), .s7_mask(4'hF),
+		.s8_addr(4'h8), .s8_mask(4'hF),	.s9_addr(4'h9), .s9_mask(4'hF),
+		.sa_addr(4'ha), .sa_mask(4'hF),	.sb_addr(4'hb), .sb_mask(4'hF),
+		.sc_addr(4'hc), .sc_mask(4'hF),	.sd_addr(4'hd), .sd_mask(4'hF),
+		.se_addr(4'he), .se_mask(4'hF),	.sf_addr(4'hf), .sf_mask(4'hF))
+   wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
+
+   assign s7_ack = 0;
+   assign s8_ack = 0;   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
+   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 0, Misc LEDs, Switches, controls
+   
+   localparam REG_LEDS = 7'd0;         // out
+   localparam REG_SWITCHES = 7'd2;     // in
+   localparam REG_CGEN_CTRL = 7'd4;    // out
+   localparam REG_CGEN_ST = 7'd6;      // in
+   localparam REG_TEST = 7'd8;         // out
+   localparam REG_RX_FRAMELEN = 7'd10; // in
+   localparam REG_TX_FRAMELEN = 7'd12; // out
+   localparam REG_XFER_RATE = 7'd14;   // out
+   localparam REG_COMPAT = 7'd16;      // in
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  reg_leds <= 0;
+	  reg_cgen_ctrl <= 2'b11;
+	  reg_test <= 0;
+	  tx_frame_len <= 0;
+	  xfer_rate <= 0;
+       end
+     else
+       if(s0_cyc & s0_stb & s0_we) 
+	 case(s0_adr[6:0])
+	   REG_LEDS :
+	     reg_leds <= s0_dat_mosi;
+	   REG_CGEN_CTRL :
+	     reg_cgen_ctrl <= s0_dat_mosi;
+	   REG_TEST :
+	     reg_test <= s0_dat_mosi;
+	   REG_TX_FRAMELEN :
+	     tx_frame_len <= s0_dat_mosi;
+	   REG_XFER_RATE :
+	     xfer_rate <= s0_dat_mosi;
+	 endcase // case (s0_adr[6:0])
+
+   assign tx_enable = xfer_rate[15];
+   assign rx_enable = xfer_rate[14];
+   assign rate = xfer_rate[7:0];
+   
+   assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
+   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
+   
+   assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
+			(s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
+			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
+			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
+			(s0_adr[6:0] == REG_TEST) ? reg_test :
+			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
+			(s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+			16'hBEEF;
+   
+   assign s0_ack = s0_stb & s0_cyc;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 1, UART
+   //    depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock
+   
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart 
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack),
+      .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
+      .rx_int_o(),.tx_int_o(),
+      .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o());
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 2, SPI
+
+   spi_top16 shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
+      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
+      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Slave 3, I2C
+
+   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   i2c_master_top #(.ARST_LVL(1)) i2c 
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+      .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
+      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+      .wb_ack_o(s3_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_miso[15:8] = 8'd0;
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+
+   wire [31:0] 	atr_lines;
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   
+   nsgpio16LE 
+     nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
+		.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
+		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		.gpio( {io_tx,io_rx} ) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #5
+
+   // only have 32 regs, 32 bits each with current setup...
+   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi),
+      .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller -- Slave #6
+
+   atr_controller16 atr_controller16
+     (.clk_i(wb_clk), .rst_i(wb_rst),
+      .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
+      .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
+      .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
+
+
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Debug circuitry
+
+   assign debug_clk = { EM_CLK, clk_fpga };
+
+   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
+		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
+		    { EM_D } };
+
+   assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, 
+			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
+
+   assign debug_gpio_1 = debug_vt;
+   
+/*   
+   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
+			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
+			   {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
+			   {2'b0, bus_error, debug_gpmc[4:0] },
+			   {misc_gpio[7:0]} };
+  */ 
+endmodule // u1e_core
diff --git a/usrp2/top/u1e_ethdebug/.gitignore b/usrp2/top/u1e_ethdebug/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/usrp2/top/u1e_ethdebug/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e_ethdebug/Makefile b/usrp2/top/u1e_ethdebug/Makefile
new file mode 100644
index 000000000..751b52970
--- /dev/null
+++ b/usrp2/top/u1e_ethdebug/Makefile
@@ -0,0 +1,83 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e.v \
+u1e.ucf
+
+SOURCES = $(abspath $(TOP_SRCS))
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf
new file mode 100644
index 000000000..d6a2ea4ed
--- /dev/null
+++ b/usrp2/top/u1e_ethdebug/u1e.ucf
@@ -0,0 +1,88 @@
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+#NET "EM_NBE<1>"  LOC = "D14"  ;
+#NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+NET "overo_gpio64"  LOC = "A4"  ;  # nRESET
+NET "overo_gpio176"  LOC = "B4"  ;  # IRQ
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v
new file mode 100644
index 000000000..2a543a313
--- /dev/null
+++ b/usrp2/top/u1e_ethdebug/u1e.v
@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+//`define DCM 1
+
+module u1e
+  (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb,
+
+   // GPMC
+   input EM_CLK, input [15:0] EM_D, input [10:1] EM_A,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE,
+   input EM_NADV_ALE,
+
+   input overo_gpio64, input overo_gpio176
+   );
+
+   assign debug_clk = {EM_CLK, EM_NADV_ALE};
+
+   assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb};
+
+   assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE },
+		    { EM_A[10], EM_A[7:1] },
+		    { EM_D[15:8] },
+		    { EM_D[7:0] } };
+   
+
+endmodule // u1e
diff --git a/usrp2/top/u1e_passthru/.gitignore b/usrp2/top/u1e_passthru/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/usrp2/top/u1e_passthru/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile
new file mode 100644
index 000000000..d1950629b
--- /dev/null
+++ b/usrp2/top/u1e_passthru/Makefile
@@ -0,0 +1,99 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = passthru
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+passthru.v \
+passthru.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf
new file mode 100644
index 000000000..64e6f0440
--- /dev/null
+++ b/usrp2/top/u1e_passthru/passthru.ucf
@@ -0,0 +1,6 @@
+NET "overo_gpio145"  LOC = "C7"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+NET "fpga_cfg_din"  LOC = "W17"  ;
+NET "fpga_cfg_cclk"  LOC = "V17"  ;
diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v
new file mode 100644
index 000000000..12e4db017
--- /dev/null
+++ b/usrp2/top/u1e_passthru/passthru.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module passthru
+  (input overo_gpio145,
+   output cgen_sclk,
+   output cgen_sen_b,
+   output cgen_mosi,
+   input fpga_cfg_din,
+   input fpga_cfg_cclk
+   );
+   
+   assign cgen_sclk = fpga_cfg_cclk;
+   assign cgen_sen_b = overo_gpio145;
+   assign cgen_mosi = fpga_cfg_din;
+   
+   
+endmodule // passthru