uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
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\| * \| \| \| \|	debug pins	Matt Ettus	2010-06-10	1	-3/+6
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\| * \| \| \| \|	much bigger fifos	Matt Ettus	2010-06-10	1	-2/+2
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\| * \| \| \| \|	proper overrun, underrun connections, debug pins.	Matt Ettus	2010-06-10	1	-4/+8
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\| * \| \| \| \|	ignores	Matt Ettus	2010-06-08	1	-0/+1
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\| * \| \| \| \|	debug pins	Matt Ettus	2010-06-08	1	-1/+2
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\| * \| \| \| \|	Merge branch 'master' into u1e	Matt Ettus	2010-06-08	2	-2/+2
\| \|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: allow other clock rates in vita time report ise version in build proper name for directory name build directory with ISE version name
\| * \| \| \| \| \|	remove double declaration	Matt Ettus	2010-06-06	1	-1/+1
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\| * \| \| \| \| \|	use fifo19 not fifo18 in makefile	Matt Ettus	2010-06-06	1	-1/+1
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\| * \| \| \| \| \|	Phil wants gpio #145	Matt Ettus	2010-06-03	2	-4/+4
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\| * \| \| \| \| \|	use same version as usrp2-udp, so regs are same place in memory map	Matt Ettus	2010-06-01	2	-2/+2
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\| * \| \| \| \| \|	Merge branch 'ise12_exp' into u1e	Matt Ettus	2010-06-01	4	-160/+1218
\| \|\ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
\| \| * \| \| \| \| \|	zero out debug pins. helps timing a little bit.	Matt Ettus	2010-06-01	1	-9/+11
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\| \| * \| \| \| \| \|	Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵	Matt Ettus	2010-05-28	2	-30/+28
\| \| \|\ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
\| \| \| * \| \| \| \| \|	experimental mods to make ram loader fully synchronous. Based on IJB's work	Matt Ettus	2010-05-26	1	-15/+14
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\| \| * \| \| \| \| \| \|	Merge branch 'master_nocache' into master_nocache_post_merge	Matt Ettus	2010-05-28	4	-15/+20
\| \| \|\ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
\| \| \| * \| \| \| \| \| \|	change the debug pins, which makes it more reliable. This is unnerving.	Matt Ettus	2010-05-26	1	-1/+2
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\| \| \| * \| \| \| \| \|	fixes from IJB from 5/24. Basically connect unconnected wires.	Matt Ettus	2010-05-24	1	-2/+3
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\| \| \| * \| \| \| \| \|	removes the icache and pipelines the reads	Matt Ettus	2010-05-20	2	-5/+6
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\| * \| \| \| \| \| \| \|	connect the rx run lines so it doesn't get optimized out	Matt Ettus	2010-06-01	1	-1/+4
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\| * \| \| \| \| \| \| \|	use DDR regs instead of a 2nd clock	Matt Ettus	2010-06-01	1	-8/+46
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\| * \| \| \| \| \| \| \|	assign addresses for the settings regs	Matt Ettus	2010-06-01	1	-5/+6
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\| * \| \| \| \| \| \| \|	vita49 tx and rx added in, all sample rates now at main system clock rate.	Matt Ettus	2010-06-01	4	-107/+220
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\| * \| \| \| \| \| \| \|	Merge branch 'udp' into u1e_merge_with_udp	Matt Ettus	2010-05-27	2	-8/+8
\| \|\ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
\| * \ \ \ \ \ \ \ \	Merge branch 'master' into u1e_merge_with_master	Matt Ettus	2010-05-27	12	-2089/+20
\| \|\ \ \ \ \ \ \ \ \ \| \| \| \|_\|/ / / / / / \| \| \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
\| * \| \| \| \| \| \| \| \|	send bigger packets to reduce cpu load	Matt Ettus	2010-05-20	1	-2/+2
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\| * \| \| \| \| \| \| \| \|	put over/underrun on debug bus, remove high order address bits	Matt Ettus	2010-05-20	1	-1/+2
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\| * \| \| \| \| \| \| \| \|	Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e	Matt Ettus	2010-05-20	1	-4/+2
\| \|\ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: usrp2/top/u1e/u1e_core.v
\| \| * \| \| \| \| \| \| \| \|	better debug pins	Matt Ettus	2010-05-17	1	-6/+4
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\| * \| \| \| \| \| \| \| \| \|	combined timed and crc cases. fifo pacer produces/consumes at a fixed rate	Matt Ettus	2010-05-20	2	-34/+24
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\| * \| \| \| \| \| \| \| \|	moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵	Matt Ettus	2010-05-12	2	-22/+43
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	packet gen and test
\| * \| \| \| \| \| \| \| \|	Merge branch 'master' into u1e	Matt Ettus	2010-05-12	4	-5/+16
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\| * \| \| \| \| \| \| \| \| \|	switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵	Matt Ettus	2010-05-10	8	-561/+9
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	safe_u1e necessary.
\| * \| \| \| \| \| \| \| \| \|	proper signal level for 24 bit data	Matt Ettus	2010-05-10	1	-2/+7
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\| * \| \| \| \| \| \| \| \| \|	SPI passthru for programming clock gen chip on brand new boards	Matt Ettus	2010-05-07	3	-0/+391
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\| * \| \| \| \| \| \| \| \| \|	added DAC output pins, and a sine wave generator to test them	Matt Ettus	2010-05-04	3	-18/+63
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\| * \| \| \| \| \| \| \| \| \|	Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e	Matt Ettus	2010-05-04	2	-0/+14
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\| \| * \| \| \| \| \| \| \| \| \|	add timing constraints. Just have main clock signal at 64 MHz for now.	Matt Ettus	2010-05-04	2	-0/+14
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\| * \| \| \| \| \| \| \| \| \| \|	changed comment	Matt Ettus	2010-05-04	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \|	separate timed tx and rx instead of loopback	Matt Ettus	2010-04-28	1	-3/+51
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\| * \| \| \| \| \| \| \| \| \|	send bus error to debug pins	Matt Ettus	2010-04-26	1	-2/+4
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\| * \| \| \| \| \| \| \| \| \|	Pass previously unused GPIOs to debug pins to help debug interrupts	Matt Ettus	2010-04-24	3	-16/+21
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\| * \| \| \| \| \| \| \| \| \|	find time_64bit	Matt Ettus	2010-04-20	1	-0/+1
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\| * \| \| \| \| \| \| \| \| \|	added pps and time capability	Matt Ettus	2010-04-15	3	-5/+21
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\| * \| \| \| \| \| \| \| \| \|	access frame length regs from wishbone	Matt Ettus	2010-04-15	1	-6/+14
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\| * \| \| \| \| \| \| \| \| \|	async seems to work with packet lengths now. Still need to do wishbone regs ↵	Matt Ettus	2010-04-15	1	-3/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	for gpmc
\| * \| \| \| \| \| \| \| \| \|	async gpmc progress	Matt Ettus	2010-04-15	2	-18/+20
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\| * \| \| \| \| \| \| \| \| \|	synchronous and asynchronous gpmc models	Matt Ettus	2010-04-15	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \|	handle all tri-state in the top level of gpmc	Matt Ettus	2010-04-15	1	-0/+2
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\| * \| \| \| \| \| \| \| \| \|	more progress on synchronous interface	Matt Ettus	2010-04-14	1	-0/+1
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\| * \| \| \| \| \| \| \| \| \|	renamed to async. Will be building a sync version for GPMC_CLK	Matt Ettus	2010-04-14	1	-1/+1
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