| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵ | Matt Ettus | 2010-05-28 | 2 | -30/+28 | |
| | | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work | |||||
| | | | * | | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's work | Matt Ettus | 2010-05-26 | 1 | -15/+14 | |
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| | | * | | | | | | | Merge branch 'master_nocache' into master_nocache_post_merge | Matt Ettus | 2010-05-28 | 4 | -15/+20 | |
| | | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads | |||||
| | | | * | | | | | | | change the debug pins, which makes it more reliable. This is unnerving. | Matt Ettus | 2010-05-26 | 1 | -1/+2 | |
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| | | | * | | | | | | fixes from IJB from 5/24. Basically connect unconnected wires. | Matt Ettus | 2010-05-24 | 1 | -2/+3 | |
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| | | | * | | | | | | removes the icache and pipelines the reads | Matt Ettus | 2010-05-20 | 2 | -5/+6 | |
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| | * | | | | | | | | connect the rx run lines so it doesn't get optimized out | Matt Ettus | 2010-06-01 | 1 | -1/+4 | |
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| | * | | | | | | | | use DDR regs instead of a 2nd clock | Matt Ettus | 2010-06-01 | 1 | -8/+46 | |
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| | * | | | | | | | | assign addresses for the settings regs | Matt Ettus | 2010-06-01 | 1 | -5/+6 | |
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| | * | | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate. | Matt Ettus | 2010-06-01 | 4 | -107/+220 | |
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| | * | | | | | | | | Merge branch 'udp' into u1e_merge_with_udp | Matt Ettus | 2010-05-27 | 2 | -8/+8 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v | |||||
| | * \ \ \ \ \ \ \ \ | Merge branch 'master' into u1e_merge_with_master | Matt Ettus | 2010-05-27 | 12 | -2089/+20 | |
| | |\ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile | |||||
| | * | | | | | | | | | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 1 | -2/+2 | |
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| | * | | | | | | | | | put over/underrun on debug bus, remove high order address bits | Matt Ettus | 2010-05-20 | 1 | -1/+2 | |
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| | * | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-20 | 1 | -4/+2 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v | |||||
| | | * | | | | | | | | | better debug pins | Matt Ettus | 2010-05-17 | 1 | -6/+4 | |
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| | * | | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 2 | -34/+24 | |
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| | * | | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵ | Matt Ettus | 2010-05-12 | 2 | -22/+43 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packet gen and test | |||||
| | * | | | | | | | | | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 4 | -5/+16 | |
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| | * | | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵ | Matt Ettus | 2010-05-10 | 8 | -561/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | safe_u1e necessary. | |||||
| | * | | | | | | | | | | proper signal level for 24 bit data | Matt Ettus | 2010-05-10 | 1 | -2/+7 | |
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| | * | | | | | | | | | | SPI passthru for programming clock gen chip on brand new boards | Matt Ettus | 2010-05-07 | 3 | -0/+391 | |
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| | * | | | | | | | | | | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 3 | -18/+63 | |
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| | * | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 | |
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| | | * | | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 | |
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| | * | | | | | | | | | | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 | |
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| | * | | | | | | | | | | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 | |
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| | * | | | | | | | | | | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 | |
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| | * | | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 | |
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| | * | | | | | | | | | | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 | |
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| | * | | | | | | | | | | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 | |
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| | * | | | | | | | | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 1 | -6/+14 | |
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| | * | | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ↵ | Matt Ettus | 2010-04-15 | 1 | -3/+3 | |
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| | * | | | | | | | | | | async gpmc progress | Matt Ettus | 2010-04-15 | 2 | -18/+20 | |
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| | * | | | | | | | | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 1 | -1/+1 | |
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| | * | | | | | | | | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 1 | -0/+2 | |
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| | * | | | | | | | | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 1 | -0/+1 | |
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| | * | | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 1 | -1/+1 | |
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| | * | | | | | | | | | | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 | |
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| | * | | | | | | | | | | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 1 | -0/+3 | |
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| | * | | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 1 | -39/+7 | |
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| | * | | | | | | | | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 2 | -33/+44 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | |||||
| | * | | | | | | | | | | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 | |
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| | * | | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵ | Matt Ettus | 2010-03-26 | 3 | -8/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | be read/controlled from SW | |||||
| | * | | | | | | | | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 2 | -57/+179 | |
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| | * | | | | | | | | | | | connected spi pins, but the spi core still needs to be redone for 16 bit ↵ | Matt Ettus | 2010-03-25 | 3 | -40/+60 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs | |||||
| | * | | | | | | | | | | | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 | |
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| | * | | | | | | | | | | | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | gpmc debug pins | Matt Ettus | 2010-02-25 | 1 | -3/+6 | |
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| | * | | | | | | | | | | | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 | |
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