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| * | | | | | | | | | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
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| * | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
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| * | | | | | | | | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
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| * | | | | | | | | | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
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| * | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
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| * | | | | | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
| * | | | | | | | | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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| * | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | be read/controlled from SW
| * | | | | | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
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| * | | | | | | | | | | connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
| * | | | | | | | | | | debug pinsMatt Ettus2010-02-251-2/+3
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| * | | | | | | | | | | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
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| * | | | | | | | | | | gpmc debug pinsMatt Ettus2010-02-251-3/+6
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| * | | | | | | | | | | point to the new filesMatt Ettus2010-02-251-0/+2
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| * | | | | | | | | | | loopback and testMatt Ettus2010-02-251-2/+32
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| * | | | | | | | | | | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-253-10/+24
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| * | | | | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISE chokes on the unequal size ram
| * | | | | | | | | | | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
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| * | | | | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-222-3/+14
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| * | | | | | | | | | | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
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| * | | | | | | | | | | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
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| * | | | | | | | | | | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
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| * | | | | | | | | | | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵Matt Ettus2010-02-182-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | global set and reset module.
| * | | | | | | | | | | wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-166-9/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timing and handle wait states.
| * | | | | | | | | | | first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-165-34/+93
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| * | | | | | | | | | | copied over from safe_u1eMatt Ettus2010-02-164-0/+553
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| * | | | | | | | | | | block ram interface to GPMCMatt Ettus2010-02-161-2/+6
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| * | | | | | | | | | | basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
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| * | | | | | | | | | | reorg pin defsMatt Ettus2010-02-141-94/+102
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| * | | | | | | | | | | connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
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| * | | | | | | | | | | organized the pins in the ucf by functionMatt Ettus2010-02-091-56/+72
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| * | | | | | | | | | | builds a successful led blinkerMatt Ettus2010-02-093-2/+4
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| * | | | | | | | | | | first cut at blinking ledsMatt Ettus2010-02-094-345/+237
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| * | | | | | | | | | | skeletons that don't work yetMatt Ettus2010-02-092-0/+607
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* | | | | | | | | | | | remove old commented out codeMatt Ettus2010-11-092-184/+2
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* | | | | | | | | | | | fix timing problem on DAC output busMatt Ettus2010-11-091-2/+2
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* | | | | | | | | | | | U2P: Working ICAP bootloader. Should be ready for release.Nick Foster2010-10-081-224/+236
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* | | | | | | | | | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-071-199/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
* | | | | | | | | | | | separate the bootloader image into another fileMatt Ettus2010-10-072-204/+205
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* | | | | | | | | | | | U2P: newest bootloader with support for 32Mbit flashNick Foster2010-10-051-157/+196
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* | | | | | | | | | | | Fixed PPS. Instantiation was miscapitalized.Nick Foster2010-08-271-1/+1
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* | | | | | | | | | | | invert adc_a because it is inverted on schematic. Also clean up extraneousMatt Ettus2010-08-251-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adc signals from old adc on U2
* | | | | | | | | | | | SWAP DAC A and B, invert B to match schematicsMatt Ettus2010-08-251-3/+4
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* | | | | | | | | | | | Use new tx_policy stuff, reassigned leds to be just like U2Matt Ettus2010-08-252-36/+34
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* | | | | | | | | | | | Merge branch 'tx_policy' into u2p_txpolicyMatt Ettus2010-08-253-36/+37
|\ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * tx_policy: (21 commits) clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future rx error context packets should not be marked as errors in the fifo added compat number to usrp2 readback mux makefile dependency fix for second expansion provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host ...
| * | | | | | | | | | | clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
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| * | | | | | | | | | | Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-252-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | widened muxes to 4 bits to match tx side and handle more ADCs in future
| * | | | | | | | | | | added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
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| * | | | | | | | | | | makefile dependency fix for second expansionJosh Blum2010-08-091-1/+1
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| * | | | | | | | | | | connect the demuxMatt Ettus2010-07-281-1/+1
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