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* fpga: print timing report after generate bin fileJosh Blum2011-07-192-1/+34
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* b100: fix for fpga syntax error on xfer_rateJosh Blum2011-07-191-1/+1
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* Merge branch 'b100_shrink' into new_workJosh Blum2011-07-199-257/+306
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| * usrp2: split compat number into major/minor (increment minor for fixes)Josh Blum2011-07-032-2/+2
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| * e100: proc_int should be high when interruptedJosh Blum2011-06-201-3/+1
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| * e100: added proc_int and buffer for async messagesJosh Blum2011-06-192-17/+49
| | | | | | | | | | | | | | | | Redirected the tx_err stream into a buffer_int2, and connected interrupt when a packet is written. The proc_int is muxed into the aux spi miso to use when its not being selected for spi.
| * u1p: remove uart and bus testing to fit easierMatt Ettus2011-06-161-8/+9
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| * u1p: remove unused portsMatt Ettus2011-06-161-1/+0
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| * u1e: core compile now works as a fullchip lintMatt Ettus2011-06-161-1/+1
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| * u1p/u1e: cleanup some warnings, connect the correct clocksMatt Ettus2011-06-162-11/+10
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| * USRP2/N2x0: incremented compat numbers for frontend workJosh Blum2011-06-152-2/+2
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| * Merge branch 'usrp_e100_aux_spi' into dsp_rebaseMatt Ettus2011-06-155-156/+24
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | * usrp_e100_aux_spi: usrp-e100: removed passthrough files, not needed w/ aux spi for clock chip usrp-e100: make reg_test32 persistent across resets, bump compat number usrp-e100: work on aux spi Conflicts: usrp2/top/E1x0/u1e_core.v
| | * usrp-e100: removed passthrough files, not needed w/ aux spi for clock chipJosh Blum2011-06-093-139/+0
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| | * usrp-e100: make reg_test32 persistent across resets, bump compat numberJosh Blum2011-06-081-2/+3
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| | * usrp-e100: work on aux spiJosh Blum2011-06-082-17/+22
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| * | u1e/u1p: new register map for new dspMatt Ettus2011-06-152-26/+32
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| * | u1p: work in dual rx and frontend from u1eMatt Ettus2011-06-142-16/+61
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| * | u1p: new tx dsp frontend, copied from u1eMatt Ettus2011-06-141-10/+17
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| * | u1e-dsp: attach tx dc offset and iq balanceMatt Ettus2011-06-141-6/+9
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| * | dsp: added tx_frontend, instantiated in u2/u2pMatt Ettus2011-06-082-4/+20
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| * | u1e: update u1e to use new rx_frontend, and give it a 2nd rx dsp coreMatt Ettus2011-06-081-21/+74
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| * | u2/u2p: use all 24 bits from the rx_frontendMatt Ettus2011-06-082-2/+2
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| * | u2/u2p: use new rx_frontend in u2 and u2pMatt Ettus2011-06-082-4/+15
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| * | u2/u2p: misc connection and compilation fixesMatt Ettus2011-06-081-2/+2
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| * | u2/u2p: pull IQ balance and dcoffset out of dsp_core, put in frontend moduleMatt Ettus2011-06-081-2/+13
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* / N2XX: this method for defining R3/R4 actually worksNick Foster2011-06-103-22/+4
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* fix copyright noticeMatt Ettus2011-06-071-2/+0
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* added copyrightsJosh Blum2011-06-0712-0/+204
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* lots of renaming and moving around of toplevel directories to reflect ↵Matt Ettus2011-06-0747-1318/+0
| | | | product names
* remove old ethernet tester, no longer needed or workingMatt Ettus2011-06-074-205/+0
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* removed bit-rotted test harnessMatt Ettus2011-06-073-737/+0
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* remove old iad stuffMatt Ettus2011-06-0717-2442/+0
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* N210: added makefiles in for rev 4 versions (use LVDS)Nick Foster2011-06-076-4/+204
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* u2p: FPGA internal termination on the clock line from ADCMatt Ettus2011-06-071-2/+2
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* u2p-lvds: remove unused netsMatt Ettus2011-06-071-2/+0
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* builds nowMatt Ettus2011-06-072-2/+4
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* first cut at using lvds for adc pinsMatt Ettus2011-06-072-2/+3
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* B100: added some packet splitter debug pins, removed debug from GPIO port, ↵Nick Foster2011-05-262-6/+6
| | | | swapped I&Q in interleaver
* u1p: reset gpifMatt Ettus2011-05-261-2/+4
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* u1p: implement a signal to indicate a partially full usb lut, to flush itMatt Ettus2011-05-262-4/+9
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* u1p: need to declare wiresMatt Ettus2011-05-261-0/+1
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* u1p: vita packet generator for testing purposesMatt Ettus2011-05-261-1/+2
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* u1p: should fix underrun reportingMatt Ettus2011-05-261-1/+1
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* u1p: modify dsp_framer36 to allow it to skip the udp prot eng headers.Matt Ettus2011-05-261-1/+1
| | | | This way it works with u1e, u1p, as well as u2/u2p
* u1p: modernize, fix warnings, debug pinsMatt Ettus2011-05-261-22/+10
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* u1p: debug pinsMatt Ettus2011-05-261-2/+3
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* u1p: unused signalsMatt Ettus2011-05-261-4/+0
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* u1p: pass tx status/error packets back through GPIF over the response ↵Matt Ettus2011-05-261-12/+5
| | | | channel (short packets)
* u1p: added loopback and timed capability just like u1eMatt Ettus2011-05-262-9/+20
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* u1p: revert change to address bus widthMatt Ettus2011-05-261-2/+2
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