| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-11-11 | 1 | -0/+1 |
| * | Corrected extfifo code so that all registers that are on SRAM signals are pac... | ianb | 2010-11-11 | 1 | -32/+32 |
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-11-11 | 1 | -43/+43 |
| * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 1 | -0/+333 |
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