| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fixes from IJB from 5/24. Basically connect unconnected wires. | Matt Ettus | 2010-05-24 | 1 | -2/+3 |
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| * | removes the icache and pipelines the reads | Matt Ettus | 2010-05-20 | 1 | -5/+5 |
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| * | get rid of some warnings by declaring setting reg width | Matt Ettus | 2010-05-18 | 1 | -8/+8 |
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| * | settings bus to dsp_clk now uses clock crossing fifo | Matt Ettus | 2010-05-16 | 1 | -8/+12 |
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| * | remove port which is no longer there | Matt Ettus | 2010-05-11 | 1 | -1/+1 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 2 | -0/+805 |
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| Ettus' UHD Repository |
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