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| author | Matt Ettus <matt@ettus.com> | 2010-05-20 13:43:13 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-20 13:43:13 -0700 |
| commit | c6e8d0658dc66e9a24a87d4574c649b77ec4075d (patch) | |
| tree | 2c212b640c1f8f5d81447c3360ffaed401f4c53a /usrp2/top/u2_core | |
| parent | 621ad7cc9e68b4e304b616d8f840d3a03a047c8b (diff) | |
| download | uhd-c6e8d0658dc66e9a24a87d4574c649b77ec4075d.tar.gz uhd-c6e8d0658dc66e9a24a87d4574c649b77ec4075d.tar.bz2 uhd-c6e8d0658dc66e9a24a87d4574c649b77ec4075d.zip | |
removes the icache and pipelines the reads
Diffstat (limited to 'usrp2/top/u2_core')
| -rwxr-xr-x | usrp2/top/u2_core/u2_core.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index df74c7dba..5e0b569cc 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -284,8 +284,8 @@ module u2_core aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + .if_adr(if_adr), + .if_dat(if_dat), // Data Wishbone bus to system bus fabric .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), @@ -299,7 +299,7 @@ module u2_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), @@ -307,8 +307,8 @@ module u2_core .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), .ram_loader_done_i(ram_loader_done), - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + .if_adr(if_adr), + .if_data(if_dat), .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), |