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path: root/usrp2/top/u1e/u1e_core.v
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* move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
* no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
* match the signal names in this designMatt Ettus2010-08-231-3/+3
* debug pins cleanupMatt Ettus2010-08-231-3/+3
* properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
* attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
* connect atrMatt Ettus2010-08-171-1/+1
* connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
* enlarge loopback fifoMatt Ettus2010-08-101-4/+1
* make loopback compileMatt Ettus2010-07-141-0/+3
* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
* debug pinsMatt Ettus2010-06-101-3/+6
* much bigger fifosMatt Ettus2010-06-101-2/+2
* proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
* debug pinsMatt Ettus2010-06-081-1/+2
* remove double declarationMatt Ettus2010-06-061-1/+1
* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-011-1/+1
* connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-011-75/+129
* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| * better debug pinsMatt Ettus2010-05-171-6/+4
* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-34/+23
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* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-121-22/+39
* proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-041-2/+43
* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-241-4/+2
* added pps and time capabilityMatt Ettus2010-04-151-2/+16
* access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
* async gpmc progressMatt Ettus2010-04-151-16/+18
* added in a loopback fifoMatt Ettus2010-04-141-4/+11
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
* added 16-bit wide atr controllerMatt Ettus2010-04-011-32/+43
* connect up the 16 bit spi coreMatt Ettus2010-03-261-3/+3
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-261-3/+17
* connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-251-7/+5
* debug pinsMatt Ettus2010-02-251-2/+3
* gpmc debug pinsMatt Ettus2010-02-251-3/+6
* loopback and testMatt Ettus2010-02-251-2/+32
* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-251-6/+14
* use our fancy new debug portsMatt Ettus2010-02-231-0/+3
* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-2/+13
* GPIOs now on the wishbone interfaceMatt Ettus2010-02-221-2/+17
* added gpio control to the wishboneMatt Ettus2010-02-181-10/+13
* Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-181-27/+158
* wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-161-5/+4
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