| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | watch the ethernet chip select on our debug bus | Matt Ettus | 2010-09-23 | 1 | -1/+1 |
| * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ... | Matt Ettus | 2010-09-21 | 1 | -19/+19 |
| * | updated pins to match rev2, removed dip switch, etc. seems to compile ok. | Matt Ettus | 2010-09-09 | 1 | -129/+122 |
| * | vita49 tx and rx added in, all sample rates now at main system clock rate. | Matt Ettus | 2010-06-01 | 1 | -25/+25 |
| * | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_... | Matt Ettus | 2010-05-10 | 1 | -1/+1 |
| * | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 1 | -16/+16 |
| * | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 |
| * | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 1 | -12/+12 |
| * | added pps and time capability | Matt Ettus | 2010-04-15 | 1 | -1/+1 |
| * | connect 2 clock gen controls and 3 status pins to the wishbone so they can be... | Matt Ettus | 2010-03-26 | 1 | -5/+5 |
| * | connected spi pins, but the spi core still needs to be redone for 16 bit inte... | Matt Ettus | 2010-03-25 | 1 | -33/+39 |
| * | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 1 | -32/+32 |
| * | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 1 | -19/+19 |
| * | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 1 | -8/+6 |
| * | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 1 | -0/+262 |
