uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	this is necessary for some reason	Matt Ettus	2010-08-13	1	-1/+2
*	Merge branch 'master' into u1e_newbuild	Matt Ettus	2010-06-14	1	-206/+39
*	use fifo19 not fifo18 in makefile	Matt Ettus	2010-06-06	1	-1/+1
*	use same version as usrp2-udp, so regs are same place in memory map	Matt Ettus	2010-06-01	1	-1/+1
*	vita49 tx and rx added in, all sample rates now at main system clock rate.	Matt Ettus	2010-06-01	1	-0/+5
*	combined timed and crc cases. fifo pacer produces/consumes at a fixed rate	Matt Ettus	2010-05-20	1	-0/+1
*	moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...	Matt Ettus	2010-05-12	1	-0/+4
*	add timing constraints. Just have main clock signal at 64 MHz for now.	Matt Ettus	2010-05-04	1	-0/+1
*	find time_64bit	Matt Ettus	2010-04-20	1	-0/+1
*	async seems to work with packet lengths now. Still need to do wishbone regs ...	Matt Ettus	2010-04-15	1	-3/+3
*	handle all tri-state in the top level of gpmc	Matt Ettus	2010-04-15	1	-0/+2
*	more progress on synchronous interface	Matt Ettus	2010-04-14	1	-0/+1
*	renamed to async. Will be building a sync version for GPMC_CLK	Matt Ettus	2010-04-14	1	-1/+1
*	minor changes to get it to synthesize	Matt Ettus	2010-04-13	1	-0/+3
*	added 16-bit wide atr controller	Matt Ettus	2010-04-01	1	-1/+1
*	connect up the 16 bit spi core	Matt Ettus	2010-03-26	1	-2/+1
*	point to the new files	Matt Ettus	2010-02-25	1	-0/+2
*	first cut at making a bidirectional 2 port ram for the gpmc data interface	Matt Ettus	2010-02-23	1	-0/+1
*	settings bus with 16 bit wishbone interface, put on the main wishbone in u1e	Matt Ettus	2010-02-22	1	-1/+1
*	GPIOs now on the wishbone interface	Matt Ettus	2010-02-22	1	-1/+1
*	first cut at gpmc <-> wb bridge, split u1e into core, top, and tb	Matt Ettus	2010-02-16	1	-1/+2
*	copied over from safe_u1e	Matt Ettus	2010-02-16	1	-0/+246