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* E100: squash E100/E110 top level workJosh Blum2012-07-166-531/+84
| | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPMC. Uses the common core for E100/B100.
* gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-161-15/+11
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* Merge branch 'maint'Josh Blum2012-07-161-1/+1
|\ | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| * e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-151-1/+1
| | | | | | | | This effectivly works around bus initial transaction issues.
* | Merge branch 'maint'Josh Blum2012-05-101-1/+1
|\| | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| * e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
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* | e100/b100: bumped compat number for timed commands mergeJosh Blum2012-04-251-1/+1
|/ | | | | There were common FPGA changes and an incompatibility. This should have been done before the merge anyhow.
* vita: moved clear register to overlap with nchan registerJosh Blum2012-04-091-1/+1
| | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
* fpga: force -include_global for custom sourcesJosh Blum2012-03-122-2/+2
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-082-2/+2
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* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-061-1/+1
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-041-22/+18
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* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-023-7/+15
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* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-011-2/+5
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* dsp rework: added double buffer interface to vita txJosh Blum2012-01-281-1/+1
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* dsp rework: moved scale and round into ddc chainJosh Blum2012-01-281-1/+1
| | | | 16to8 engine now performs only a clip from 16->8
* dsp rework: top level fixes B100/E100Josh Blum2012-01-272-4/+5
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* dsp rework: integrated custom dsp module shellsJosh Blum2012-01-273-6/+10
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* dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-271-17/+33
| | | | added user registers into each toplevel (not used yet)
* dsp rework: u2_core test implementationJosh Blum2012-01-261-2/+2
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* need more umph out of correction valuesJosh Blum2011-11-101-1/+1
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* convenience makefiles for top level projectsJosh Blum2011-11-051-0/+17
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* increase vita rx fifosize to 10, like USRP2, make things workJosh Blum2011-11-041-2/+2
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* u1e: fix unattached nets from copy-paste errorMatt Ettus2011-11-041-3/+3
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* u1e/u1p: GPIOs switched over to setting regsMatt Ettus2011-10-271-21/+26
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* 32 bit compat number for E and B seriesJosh Blum2011-10-261-5/+4
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* u1e/u1p: removed led setting regMatt Ettus2011-10-261-7/+2
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* u1p/u1e: partially redone atr and gpio redoMatt Ettus2011-10-261-11/+2
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* u1e/u1p: remove unused UARTMatt Ettus2011-10-261-11/+0
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* connect and map b100 and e100 front-panel ledsJosh Blum2011-10-111-1/+1
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* E100: GPSDO serial port level conversionNick Foster2011-09-282-2/+9
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* u1e,u1p: turn off debug pins, misc cleanupsMatt Ettus2011-09-081-21/+4
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* u1e: relax GPMC constraints, eases P&RMatt Ettus2011-09-021-10/+10
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* u1e: separate build for E100 and E110, just a different FPGAMatt Ettus2011-09-012-1/+102
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* e100: squashed work on bus implementation on GPMCJosh Blum2011-08-293-42/+24
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* e100: continuation of the atr fix to get e100 to buildJosh Blum2011-08-151-2/+2
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* B100/E100: fix ATR RX mode pins not connectedNick Foster2011-08-101-2/+2
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* appease the ISE godsMatt Ettus2011-07-191-0/+1
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* e100: proc_int should be high when interruptedJosh Blum2011-06-201-3/+1
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* e100: added proc_int and buffer for async messagesJosh Blum2011-06-192-17/+49
| | | | | | | | Redirected the tx_err stream into a buffer_int2, and connected interrupt when a packet is written. The proc_int is muxed into the aux spi miso to use when its not being selected for spi.
* u1e: core compile now works as a fullchip lintMatt Ettus2011-06-161-1/+1
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* u1p/u1e: cleanup some warnings, connect the correct clocksMatt Ettus2011-06-161-3/+3
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* Merge branch 'usrp_e100_aux_spi' into dsp_rebaseMatt Ettus2011-06-155-156/+24
|\ | | | | | | | | | | | | | | | | | | * usrp_e100_aux_spi: usrp-e100: removed passthrough files, not needed w/ aux spi for clock chip usrp-e100: make reg_test32 persistent across resets, bump compat number usrp-e100: work on aux spi Conflicts: usrp2/top/E1x0/u1e_core.v
| * usrp-e100: removed passthrough files, not needed w/ aux spi for clock chipJosh Blum2011-06-093-139/+0
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| * usrp-e100: make reg_test32 persistent across resets, bump compat numberJosh Blum2011-06-081-2/+3
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| * usrp-e100: work on aux spiJosh Blum2011-06-082-17/+22
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* | u1e/u1p: new register map for new dspMatt Ettus2011-06-151-13/+16
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* | u1p: work in dual rx and frontend from u1eMatt Ettus2011-06-141-3/+1
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* | u1e-dsp: attach tx dc offset and iq balanceMatt Ettus2011-06-141-6/+9
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* | u1e: update u1e to use new rx_frontend, and give it a 2nd rx dsp coreMatt Ettus2011-06-081-21/+74
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