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| author | Josh Blum <josh@joshknows.com> | 2011-06-08 18:55:27 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-08 18:55:27 -0700 |
| commit | 903c69ff80b0e780a49585431af14a31ed41d938 (patch) | |
| tree | f2dd5defd945842361d01a7a1c1d97c1e775375f /usrp2/top/E1x0 | |
| parent | d0a8d3253b250c472a565486544bf0e050797393 (diff) | |
| download | uhd-903c69ff80b0e780a49585431af14a31ed41d938.tar.gz uhd-903c69ff80b0e780a49585431af14a31ed41d938.tar.bz2 uhd-903c69ff80b0e780a49585431af14a31ed41d938.zip | |
usrp-e100: make reg_test32 persistent across resets, bump compat number
Diffstat (limited to 'usrp2/top/E1x0')
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 02dfd6177..b894c191a 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -53,7 +53,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd4; + wire [7:0] COMPAT_NUM = 8'd5; wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -382,8 +382,9 @@ module u1e_core wire [31:0] reg_test32; + //this setting reg is persistent across resets, to check for fpga loaded setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + (.clk(wb_clk),.rst(/*wb_rst*/1'b0),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(reg_test32),.changed()); wb_readback_mux_16LE readback_mux_32 |