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* usrp-n210: almost working w/ packet router + zpuJosh Blum2010-12-176-8/+8
* zpu: set all the address widths to 16, grumbleJosh Blum2010-12-084-5/+5
* zpu: moved stack pointer and made connection for statusJosh Blum2010-12-061-1/+1
* zpu: brought status signal out to top levelJosh Blum2010-12-061-1/+3
* zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-069-0/+1536
* reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
* u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
* need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 ...Matt Ettus2010-11-101-0/+1
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-107-119/+292
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| * Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-0/+27
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| * \ Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-11/+21
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| | * | removes the icache and pipelines the readsMatt Ettus2010-05-202-11/+21
| * | | Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27222-318/+6
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| * | | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
| * | | remove timescale junkMatt Ettus2010-03-265-21/+19
| * | | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
* | | | Fix for SPI SS > 8 bits wideNick Foster2010-07-281-2/+2
* | | | separate boot ram, redone memory map, connected uartMatt Ettus2010-07-131-2/+2
* | | | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-142-11/+21
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* | | first attempt at cleaning up the build systemMatt Ettus2010-06-101-0/+28
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* | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
* | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22331-0/+1515024
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