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* reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
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* u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
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* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-106-117/+291
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| * Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-2744-50/+0
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
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| * | remove timescale junkMatt Ettus2010-03-265-21/+19
| | | | | | | | | | | | | | | | | | | | | | | | get rid of asynchronous resets fix spelling error corrected comment
| * | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
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* | | Fix for SPI SS > 8 bits wideNick Foster2010-07-281-2/+2
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* | get rid of old CVS linkageMatt Ettus2010-05-1844-50/+0
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2257-0/+1546