Merge branch 'master' into u1e_merge_with_master

* master:
  get rid of some warnings by declaring setting reg width
  added width parameter to avoid warnings (thanks IJB) and default value parameter
  added pragmas suggested by Ian Buckley to help ISE12 synthesis
  get rid of old CVS linkage
  settings bus to dsp_clk now uses clock crossing fifo
  remove files for old prototypes, they were confusing people
  revert commit 9899b81f920 which should have improved timing but didn't

Conflicts:
	usrp2/control_lib/setting_reg.v
	usrp2/top/u2_core/u2_core.v
	usrp2/top/u2_rev3/Makefile

44 files changed, 0 insertions, 50 deletions

diff --git a/usrp2/opencores/spi/CVS/Entries b/usrp2/opencores/spi/CVS/Entries
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-D/bench////
-D/doc////
-D/rtl////
-D/sim////
diff --git a/usrp2/opencores/spi/CVS/Repository b/usrp2/opencores/spi/CVS/Repository
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-spi
diff --git a/usrp2/opencores/spi/CVS/Root b/usrp2/opencores/spi/CVS/Root
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diff --git a/usrp2/opencores/spi/CVS/Template b/usrp2/opencores/spi/CVS/Template
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diff --git a/usrp2/opencores/spi/bench/CVS/Entries b/usrp2/opencores/spi/bench/CVS/Entries
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diff --git a/usrp2/opencores/spi/bench/CVS/Repository b/usrp2/opencores/spi/bench/CVS/Repository
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-spi/bench
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diff --git a/usrp2/opencores/spi/bench/CVS/Template b/usrp2/opencores/spi/bench/CVS/Template
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diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Entries b/usrp2/opencores/spi/bench/verilog/CVS/Entries
deleted file mode 100644
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-/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003//
-/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004//
-/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002//
-D
diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Repository b/usrp2/opencores/spi/bench/verilog/CVS/Repository
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diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Root b/usrp2/opencores/spi/bench/verilog/CVS/Root
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diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Template b/usrp2/opencores/spi/bench/verilog/CVS/Template
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diff --git a/usrp2/opencores/spi/doc/CVS/Entries b/usrp2/opencores/spi/doc/CVS/Entries
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-/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/
-D/src////
diff --git a/usrp2/opencores/spi/doc/CVS/Repository b/usrp2/opencores/spi/doc/CVS/Repository
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-/spi.doc/1.7/Mon Mar 15 17:46:06 2004/-kb/
-D
diff --git a/usrp2/opencores/spi/doc/src/CVS/Repository b/usrp2/opencores/spi/doc/src/CVS/Repository
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diff --git a/usrp2/opencores/spi/rtl/CVS/Entries b/usrp2/opencores/spi/rtl/CVS/Entries
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diff --git a/usrp2/opencores/spi/rtl/CVS/Root b/usrp2/opencores/spi/rtl/CVS/Root
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diff --git a/usrp2/opencores/spi/rtl/CVS/Template b/usrp2/opencores/spi/rtl/CVS/Template
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diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/opencores/spi/rtl/verilog/CVS/Entries
deleted file mode 100644
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--- a/usrp2/opencores/spi/rtl/verilog/CVS/Entries
+++ /dev/null
@@ -1,6 +0,0 @@
-/spi_clgen.v/1.3/Thu Jul  3 17:32:15 2003//
-/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004//
-/spi_shift.v/1.7/Tue Jul  8 15:36:37 2003//
-/spi_top.v/1.8/Tue Jul  8 15:36:37 2003//
-/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002//
-D
diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/opencores/spi/rtl/verilog/CVS/Repository
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diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Root b/usrp2/opencores/spi/rtl/verilog/CVS/Root
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diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Template b/usrp2/opencores/spi/rtl/verilog/CVS/Template
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-D/rtl_sim////
-D/run////
diff --git a/usrp2/opencores/spi/sim/CVS/Repository b/usrp2/opencores/spi/sim/CVS/Repository
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diff --git a/usrp2/opencores/spi/sim/CVS/Template b/usrp2/opencores/spi/sim/CVS/Template
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diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository
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diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root
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diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
deleted file mode 100644
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--- a/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
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diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries
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+++ /dev/null
@@ -1,4 +0,0 @@
-/rtl.fl/1.1/Mon Mar 15 17:46:08 2004//
-/run_sim/1.1/Mon Mar 15 17:46:08 2004//
-/sim.fl/1.1/Mon Mar 15 17:46:08 2004//
-D
diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository
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