uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merge branch 'master' into u1e_merge_with_master	Matt Ettus	2010-05-27	44	-50/+0
\|\ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
\| *	get rid of old CVS linkage	Matt Ettus	2010-05-18	44	-50/+0
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* \|	16 bit wide spi core	Matt Ettus	2010-03-27	1	-0/+182
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* \|	remove timescale junk	Matt Ettus	2010-03-26	5	-21/+19
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	get rid of asynchronous resets fix spelling error corrected comment
* \|	remove the #1 delay in all the regs. They just slow down sims.	Matt Ettus	2010-02-22	4	-96/+90
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*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	57	-0/+1546