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path: root/usrp2/opencores/spi/rtl/verilog
Commit message (Expand)AuthorAgeFilesLines
* reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
* u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-106-117/+291
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| * Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-274-8/+0
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| * | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
| * | remove timescale junkMatt Ettus2010-03-265-21/+19
| * | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
* | | Fix for SPI SS > 8 bits wideNick Foster2010-07-281-2/+2
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* | get rid of old CVS linkageMatt Ettus2010-05-184-8/+0
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-229-0/+802