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* separate boot ram, redone memory map, connected uartMatt Ettus2010-07-131-2/+2
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* barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-142-11/+21
| | | | seem to work ok
* added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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* get rid of old CVS linkageMatt Ettus2010-05-1833-73/+0
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2254-0/+3583