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* E100: revert unnecessary change to fifo_to_gpmcJosh Blum2013-05-091-3/+7
| | | | | This change was intended to remove warnings as only 16 bits of the FIFO bus are used. However this change has unintentional consequences for receive performance.
* e100: switch to fixed length xfersJosh Blum2013-03-143-33/+34
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* e100: tighten timing - less routing on EM_AJosh Blum2012-07-192-2/+2
| | | | | There were a few places it was ok to use addr over EM_A. This makes routing sligtly easier for GPMC signals.
* e100: renamed top level for E100/E110 to E1x0Josh Blum2012-07-171-7/+7
| | | | Some minor tweaks to gpmc_to_fifo + timing
* gpmc: squashed GPMC FIFO work for E100Josh Blum2012-07-165-162/+93
| | | | | The control and data slaves are now both implemented as FIFOs. Requires another squash of E100 top level to use.
* gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-161-11/+26
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* e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-151-4/+4
| | | | This effectivly works around bus initial transaction issues.
* e100: reverted commit registering in gpmcJosh Blum2012-07-151-38/+1
| | | | There is a subtle bus issue that the last changset did not address.
* Added registers for gpmc-to-fifo interface to address sequence errors for ↵Al Fayez2012-05-221-1/+38
| | | | E100/E110
* fpga: xclock fix for edge case conditionJosh Blum2012-05-081-6/+8
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* e100: squashed work on bus implementation on GPMCJosh Blum2011-08-2919-942/+521
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* added copyrightsJosh Blum2011-06-0711-0/+187
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* fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-252-6/+3
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* timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-251-1/+11
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* u1e: hook up tester controlsMatt Ettus2011-02-171-5/+7
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* move declarations to before useMatt Ettus2011-02-161-8/+8
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* hook up under/overruns for debug purposesMatt Ettus2011-02-161-5/+5
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* e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-161-5/+89
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* allow for CS to rise before, at the same time, or after OEMatt Ettus2010-09-241-7/+6
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* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-172-16/+16
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* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-0/+20
| | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
* debug pinsMatt Ettus2010-06-082-3/+8
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* added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵Matt Ettus2010-06-062-4/+4
| | | | is LE.
* get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-062-4/+6
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* moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-121-38/+53
| | | | packet gen and test
* have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO
* Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
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* Register outputs to omap to prevent runt pulses from falsely triggering ↵Matt Ettus2010-04-233-7/+20
| | | | interrupts
* access frame length regs from wishboneMatt Ettus2010-04-151-4/+4
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* async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-153-22/+35
| | | | for gpmc
* async gpmc progressMatt Ettus2010-04-152-0/+153
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* add bus error reportingMatt Ettus2010-04-151-3/+9
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* correct name of moduleMatt Ettus2010-04-151-2/+2
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* progress on synchronous gpmc, but it may not be possible due to the limited ↵Matt Ettus2010-04-153-43/+45
| | | | number of clock edges
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-152-6/+6
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* more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
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* more progress on synchronous interfaceMatt Ettus2010-04-143-26/+94
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* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-2/+2
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* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
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* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
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* minor changes to get it to synthesizeMatt Ettus2010-04-131-1/+1
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* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-122-81/+110
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* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
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* gpmc debug pinsMatt Ettus2010-02-251-1/+8
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* fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
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* corrected logicMatt Ettus2010-02-251-17/+7
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* edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
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* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-252-11/+122
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* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-6/+18
| | | | ISE chokes on the unequal size ram
* speed up the presentation of registered wb data to the gpmcMatt Ettus2010-02-171-2/+5
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