| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | packet_router: created packet dispatcher component to replace packet inspecto... | Josh Blum | 2011-03-08 | 3 | -236/+293 |
| * | first cut at 36:72 and 72:36 for extra wide fifos. untested | Matt Ettus | 2011-03-07 | 2 | -0/+188 |
| * | u2/u2p: proper connections for dsp_framer | Matt Ettus | 2011-03-07 | 1 | -1/+0 |
| * | u2/u2p: fix off-by-one error in dsp_framer | Matt Ettus | 2011-03-06 | 1 | -1/+2 |
| * | u2/u2p: removed redundant shortfifos from udp path (they are in the size adap... | Matt Ettus | 2011-03-05 | 1 | -17/+5 |
| * | u2/u2p: moved dsp framer into vita_rx_chain | Matt Ettus | 2011-03-05 | 1 | -23/+5 |
| * | u2/u2p: rework ports again | Matt Ettus | 2011-03-04 | 1 | -3/+3 |
| * | u2/u2p: reworked port names on packet_router | Matt Ettus | 2011-03-04 | 1 | -3/+3 |
| * | u2/u2p: reworked dsp framer to work more like a fifo, and do vita length corr... | Matt Ettus | 2011-03-04 | 1 | -87/+56 |
| * | u2/u2p: allow cpu to receive or send packets longer than the buffer size. | Matt Ettus | 2011-03-04 | 1 | -7/+10 |
| * | make fifo36_to_ll8 properly handle partial end lines. | Matt Ettus | 2011-03-04 | 2 | -152/+31 |
| * | Merge branch 'gpmc_testing' into ethfifo_reorg | Matt Ettus | 2011-03-03 | 9 | -12/+307 |
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| | * | timed packet generator : Temporarily use a checksum rather than a crc to vali... | Philip Balister | 2011-02-26 | 1 | -3/+9 |
| | * | correct port names | Matt Ettus | 2011-02-25 | 1 | -2/+2 |
| | * | fifo36_mux now has shortfifos on the input ports as well as output | Matt Ettus | 2011-02-25 | 1 | -12/+25 |
| | * | e100: integrate loopback and timed testing into main image | Matt Ettus | 2011-02-16 | 3 | -2/+22 |
| | * | Fix endianess for packet length and sequence number for e100 timed image. | Philip Balister | 2011-02-16 | 1 | -8/+8 |
| | * | put these files in the right place. newfifo is long gone. | Matt Ettus | 2011-02-16 | 8 | -0/+256 |
| * | | all: removed old unused fifos | Matt Ettus | 2011-03-03 | 2 | -21/+1 |
| * | | all: short fifos on front and back of fifo36_to_fifo19 | Matt Ettus | 2011-03-03 | 1 | -15/+33 |
| * | | u2/u2p: shortfifos in fifo36_to_ll8, no more _n junk | Matt Ettus | 2011-03-03 | 1 | -28/+43 |
| * | | u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdsp | Matt Ettus | 2011-03-03 | 1 | -7/+10 |
| * | | u2/u2p: switch over to 36 bit wide ethernet wrapper | Matt Ettus | 2011-03-03 | 1 | -27/+47 |
| * | | ethfifo_reorg: switch buffer int2 lastline to work as a length parameter | Josh Blum | 2011-03-03 | 1 | -5/+6 |
| * | | u2/u2p: get rid of redeclaration | Matt Ettus | 2011-03-03 | 1 | -1/+0 |
| * | | u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapper | Matt Ettus | 2011-03-03 | 1 | -8/+6 |
| * | | u2/u2p: short fifos put on both sides of ll8_to_fifo19 | Matt Ettus | 2011-03-03 | 1 | -27/+44 |
| * | | u2/u2p: inserted short fifo into the packet inspector path to help routing an... | Matt Ettus | 2011-02-17 | 1 | -1/+13 |
| * | | added port_sel param to dsp framer | Josh Blum | 2011-02-17 | 2 | -4/+5 |
| * | | packet_router: added support for two dsps into router | Josh Blum | 2011-02-15 | 1 | -14/+20 |
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| * | believed to fix fifo swizzling with partially empty lines | Matt Ettus | 2011-01-21 | 3 | -25/+114 |
| * | xbar and valve: fix switching delayed by active signal | Josh Blum | 2011-01-11 | 2 | -9/+12 |
| * | packet_router: tweak mode SR (its only 1 bit) | Josh Blum | 2011-01-07 | 1 | -3/+2 |
| * | usrp2: removed unused changed signal for mode selection | Josh Blum | 2010-12-29 | 1 | -2/+1 |
| * | packet_router: replace buffers interfaced in packet router with buffer_int2 | Josh Blum | 2010-12-28 | 3 | -163/+25 |
| * | now uses 2 rams, one for read, one for write | Matt Ettus | 2010-12-28 | 1 | -89/+97 |
| * | reformatting | Matt Ettus | 2010-12-28 | 1 | -5/+1 |
| * | first cut at new buffer interface for CPU. Like old buffer_int plus | Matt Ettus | 2010-12-28 | 1 | -0/+169 |
| * | unused line | Matt Ettus | 2010-12-28 | 1 | -1/+0 |
| * | packet_router: use the mode register to reset hs control and cpu sms | Josh Blum | 2010-12-27 | 1 | -22/+13 |
| * | packet_router: all non ip/udp should also go to both | Josh Blum | 2010-12-13 | 1 | -7/+5 |
| * | packet_router: harmless logic tweaks | Josh Blum | 2010-12-12 | 2 | -11/+8 |
| * | packet_router: reverted enable change to dsp framer, it was already correct | Josh Blum | 2010-12-12 | 1 | -2/+1 |
| * | packet_router: raise enable for bram reads the cycle before as well | Josh Blum | 2010-12-11 | 2 | -2/+4 |
| * | packet_router: added fifo before cpu_out, tweaked inspection logic | Josh Blum | 2010-12-10 | 1 | -25/+29 |
| * | packet_router: gave the inspector a 4th output which is CPU only | Josh Blum | 2010-12-10 | 1 | -83/+123 |
| * | packet_router: added status readback for mode, incremented compat number | Josh Blum | 2010-11-24 | 1 | -0/+1 |
| * | packet_router: split the control register into misc, cpu hs out, cpu hs inp | Josh Blum | 2010-11-24 | 1 | -10/+24 |
| * | packet_router: modification for sequence number and vrt header offset | Josh Blum | 2010-11-23 | 1 | -1/+1 |
| * | packet_router: it makes more sense to connect the control flags this way now | Josh Blum | 2010-11-23 | 1 | -13/+6 |
