uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	these got dropped during the rebase	Matt Ettus	2010-11-11	4	-31/+37
*	1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu...	Ian Buckley	2010-11-11	10	-0/+544
*	Added external RAM FIFO to u2plus.	Ian Buckley	2010-11-11	12	-3/+4206
*	Regenerated FIFO with lower trigger level for almost full flag to reflect log...	Ian Buckley	2010-11-11	4	-9/+9
*	Regenerated FIFO's for extfifo.	Ian Buckley	2010-11-11	11	-726/+15
*	Adding in files that probably didn;t exist in the ISE10.1 version of coregen	Ian Buckley	2010-11-11	5	-0/+808
*	Bringing all coregen files checked in into sync	Ian Buckley	2010-11-11	10	-137/+60
*	Found bug due to not accounting for the correct number of possible in flight ...	Ian Buckley	2010-11-11	4	-42/+50
*	checkin of generated coregen files	Matt Ettus	2010-11-11	18	-8/+556
*	External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...	Ian Buckley	2010-11-11	4	-15/+23
*	Checkpoint checkin.	Ian Buckley	2010-11-11	4	-0/+494
*	first attempt at cleaning up the build system	Matt Ettus	2010-06-10	1	-0/+19
*	allow settings bus to cross to a new clock domain, should help timing, but no...	Matt Ettus	2010-05-11	8	-0/+514
*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	48	-0/+3055