| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added external RAM FIFO to u2plus. | Ian Buckley | 2010-11-11 | 1 | -3/+3 |
| | | | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3 | ||||
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵ | Ian Buckley | 2010-11-11 | 1 | -10/+12 |
| | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. | ||||
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 1 | -0/+20 |
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| Ettus' UHD Repository |
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