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| author | Ian Buckley <ian.buckley@gmail.com> | 2010-10-15 11:37:23 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:35 -0800 |
| commit | 7e75951d263c00e9f84bdf14d6176680cb3de833 (patch) | |
| tree | bf5fd721b3c287b9a2a62d0664e2c107fee6eafc /usrp2/coregen/coregen.cgp | |
| parent | 8507271de44aadc564354a77c8b9259e24f0d246 (diff) | |
| download | uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.tar.gz uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.tar.bz2 uhd-7e75951d263c00e9f84bdf14d6176680cb3de833.zip | |
Added external RAM FIFO to u2plus.
Added code branch to ext_fifo.v using generate that instantiates
different input and out fifo's and touched nobl_fifo code so that it
works at 18 and 36bit widths.
Added 2nd DCM to top level to generate off chip RAMCLK.
Added explicit I/O instances to top level for tristate drivers and
changed signals to core as needed.
Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
Diffstat (limited to 'usrp2/coregen/coregen.cgp')
| -rw-r--r-- | usrp2/coregen/coregen.cgp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index 4c9201aff..dd85a7f50 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,4 +1,4 @@ -# Date: Mon Jul 26 21:55:33 2010 +# Date: Fri Oct 15 07:50:19 2010 SET addpads = false SET asysymbol = false @@ -13,10 +13,10 @@ SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 SET removerpms = false -SET simulationfiles = Behavioral +SET simulationfiles = Structural SET speedgrade = -5 SET verilogsim = true SET vhdlsim = false SET workingdirectory = /tmp/ -# CRC: 394da717 +# CRC: 983b9b45 |