| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
| * | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
| * | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| | * | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
| * | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+44 |
| * | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 1 | -0/+54 |
| * | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
| * | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 76 | -0/+11382 |
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