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* u2: redo the atr gpio pins, remove some old cruftMatt Ettus2011-07-271-45/+31
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* appease the ISE godsMatt Ettus2011-07-192-2/+2
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* removed wb readback of ATR, allowing it to be synthesized as lutsMatt Ettus2011-07-192-4/+10
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* added copyrightsJosh Blum2011-06-0760-0/+1020
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* u1p: fix bus widths and other warningsMatt Ettus2011-05-261-11/+11
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* modernize the make files, it now compiles. not tested.Matt Ettus2011-05-261-0/+1
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* select bus is 2 bits wideNick Foster2011-05-261-1/+1
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* add padding into gpif response pathMatt Ettus2011-05-261-1/+7
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* pad out packets to a minimum lengthMatt Ettus2011-05-261-1/+10
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* fixed length command packetsMatt Ettus2011-05-261-1/+1
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* give response packets the same format as tx packetsMatt Ettus2011-05-261-1/+13
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* successful testMatt Ettus2011-05-261-0/+104
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* old and unusedMatt Ettus2011-05-261-151/+0
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* fifo to wb should be functionally complete, needs testingMatt Ettus2011-05-261-21/+141
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* added a loopback control port, will do full wishbone interface laterMatt Ettus2011-05-261-0/+34
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* N210: bootram expanded to 16KB (8 BRAMs) and UDP bootloader addedNick Foster2011-04-211-98/+143
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* Merge branch 'master' into nextMatt Ettus2011-03-272-2/+2
|\ | | | | | | | | | | | | * master: u2p: N200 Makefile u1e: use icarus verilog for lint clean up a bunch of warnings and incorrect bus widths
| * clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-162-2/+2
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* | u2/u2p: reworked settings bus addressesMatt Ettus2011-03-161-3/+1
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* put these files in the right place. newfifo is long gone.Matt Ettus2011-02-168-256/+0
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-0/+5
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* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-142-0/+74
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1014-18/+623
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| * Merge branch 'ise12' into u1eMatt Ettus2010-07-191-0/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
| * \ Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1421-7499/+47
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
| * | | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
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| * | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵Matt Ettus2010-06-062-37/+47
| | | | | | | | | | | | | | | | is LE.
| * | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-061-40/+0
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| * | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-212/+317
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * \ \ Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-282-220/+252
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | | * | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-262-220/+252
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| | * | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-281-0/+73
| | |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | | * | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-0/+2
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| | | * | | removes the icache and pipelines the readsMatt Ettus2010-05-201-0/+71
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| * | | | | Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-271-2/+4
| |\ \ \ \ \ | | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | test full width packetsMatt Ettus2010-05-241-0/+27
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| * | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | (by design)
| * | | | | fix double declarationMatt Ettus2010-05-211-1/+0
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| * | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-1/+1
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| * | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+24
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| * | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-123-6/+48
| | | | | | | | | | | | | | | | | | | | | | | | packet gen and test
| * | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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| * | | | | Merge branch 'master' into u1eMatt Ettus2010-05-123-14/+26
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| * | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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| * | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-013-14/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
| * | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-253-50/+51
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| * | | | | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
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| * | | | | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
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| * | | | | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
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| * | | | | | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: .gitignore
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