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* mpm: rh: Add MAX 10 update scriptAlex Williams2018-11-071-0/+165
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* rh: add lo distribution supportMark Meserve2018-11-052-3/+144
| | | | | | | | | - This is a combination of 5 commits. - rh: add lo distribution board gpio expander - rh: add lo distribution mpm functions - rh: add code to conditionally initialize lo distribution - rh: change empty i2c device from exception to assertion - rh: add lo distribution board control
* rh: disable lmk test outputMark Meserve2018-10-301-1/+1
| | | | - Improves spur performance
* rh: Phase DAC configuration clean-upHumberto Jimenez2018-10-301-6/+4
| | | | | | | | | | | | | | | | | | | | | - Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code.
* rh: Deterministic latency optimization in JESD204BHumberto Jimenez2018-10-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Optimized JESD204B RX/TX links' latency. - Made JESD latency constant across supported frequencies. - Checking RX SYSREF capture in the FPGA deframer block. The JESD204B standard can be linked in such a way to produce a repeatable, deterministic delay from the framer to deframer. This is accomplished by setting up a LMFC (local multiframe clock) in both devices. The LMFCs are reset whenever a SYSREF edge is captured by the framer and deframer. Therefore, it is simple to control the LMFC rising edges in each device by implementing variable delay elements on the SYSREF pulses to the framer and deframer. Latency across the JESD204B TX/RX links should remain constant and deterministic across the supported sampling_clock_rate values. By testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with different delay values in the FPGA, one may decrease the latency and provide enough setup and hold margin for the data to be transfered through each JESD link. It was found that a different set of SYSREF delay values are required for sampling_clock_rate = 400 MSPS to match the latency of the other supported rates.
* rh: add support for rhodium devicesMark Meserve2018-10-2510-0/+2520
| | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ni.com>
* nijesdcore: add variable configuration supportMark Meserve2018-10-252-2/+8
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* mg: adding skip_rfic argumentTrung Tran2018-10-181-2/+3
| | | | | | This change to add skip_rfic as an device argument. skip_rfic should be only used in ref_clock bist tests to bring down the test time.
* mpm: identify sysfs gpios more genericallyMark Meserve2018-10-181-1/+1
| | | | | - Allow generic path names to be given for each search parameter instead of only checking the label
* N310: Clarify logging for when re-inits occurTrung Tran2018-10-161-0/+2
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* mpm: dboard_manager: add more args to update_ref_clock_freqTrung Tran2018-10-122-2/+3
| | | | | | | | | | | | | | | Summary: This change will allow correct args to pass from mboard to dboards, that in turn can be useful for dboard manager. Details: In N310, the dboard manager needs the time source to be updated before calling update_ref_clock_source(), because it will trigger a reinit of the dboard, for which the time_source is essential to determine correct clock synchronizer settings. The special case is the white rabbit time source needs a different internal ref_clock_frequency for the clock synchronizer than the passed in ref_clock_freq.
* mpm: mg: move init_rf_cal before JESD de/framer bringupTrung Tran2018-08-161-4/+4
| | | | This sequence is the one as described by the AD9371 user guide.
* e320: Add all 5 temp sensors, fan sensor and rssi sensors per channelSugandha Gupta2018-08-091-4/+2
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* mpm: n3xx: clocking API changes for transitioning clock and time sourcesDaniel Jepson2018-08-022-4/+81
| | | | | | Added set_sync_source method to set both the time and clock sources without forcing a re-init twice. Modified the existing set_time_source and set_clock_source methods to call into set_sync_source.
* mpm: mg: periphs: Modify AD9361 reset function to keep it in resetMartin Braun2018-08-021-2/+9
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* uio: mpm: Fixup for opening mboard-regs UIOBrent Stapleton2018-07-231-13/+13
| | | | | | | | | - Fix the syntax to open mboard-regs UIO objects, and change the open() and close() functions to be private. - We were calling open() twice in every context manager line- once manually, and once in __enter__. This commit corrects those usages, and allows the context manager to fully manage the opening and closing of UIO objects.
* e320: mpm: Add dboard and mboard sensorsSugandha Gupta2018-07-181-13/+57
| | | | | | | | Adding the following sensors: - Catalina temperature, RSSI, and LO Lock sensors - GPS lock, time, TPV, and SKY sensors Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
* mpm: initial commit of E320 codeBrent Stapleton2018-07-183-4/+286
| | | | Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
* mpm: mg: Adding fast-reinit modeMartin Braun2018-07-172-19/+99
| | | | | | | | | | When a device is re-initialized without any changes (e.g., master_clock_rate, ref_clock_freq) then we can skip the initialization sequence and move on. This shaves a significant amount of time from the init sequence. Fast re-init can be overridden by providing the `force_reinit=1` device arg.
* mpm: mg: Move RF cal initialization after JESD initMartin Braun2018-07-171-2/+1
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* mpm: mg: Store init args between runsMartin Braun2018-07-171-2/+6
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* mpm: n3xx: mg: Refactor init codeMartin Braun2018-07-173-499/+583
| | | | | | | All code relevant to initializing an N310/N300 daughterboard is moved to its own module (mg_init.py). No functional changes.
* mpm: mg: Print AD9371 info as debug message during initMartin Braun2018-07-171-0/+8
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* mpm: dboard_manager: Fix docstring for get_serial()Martin Braun2018-06-181-1/+2
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* mpm: allow multiple spi device objects to use the same chip selectMark Meserve2018-05-141-2/+2
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* mpm: replace long execution function with async callTrung N Tran2018-04-301-5/+10
| | | | | | - Replace mykonos finish_initialization with async version - Replace myknonos setup_cal with async version - Remove disable_timeout on rpc_server init()
* mg: implement digital loopback arg for the rficDaniel Jepson2018-04-101-1/+6
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* n3xx: add White Rabbit supportDaniel Jepson2018-03-301-3/+17
| | | | Reviewed-by: Martin Braun <martin.braun@ettus.com>
* lmk: clean up logging statementsdjepson12018-03-071-2/+2
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* tdc: support for tdc 2.0djepson12018-03-073-35/+55
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* mpm: Fix some Pylint warningsMartin Braun2018-03-062-11/+12
| | | | No functional changes.
* mpm: Demote some log messagesMartin Braun2018-03-065-22/+21
| | | | | | The log output at level 'INFO' was pretty cluttered. This cleans up the log messages at the higher levels. In some cases, log message typos or capitalizations were also fixed.
* mpm: Rename n310 to n3xxMartin Braun2018-03-051-1/+1
| | | | | This module (and class) are, in fact, used for all N3xx-derivates so renaming it is the more correct thing to do.
* mpm: Update all license headersMartin Braun2018-02-1910-18/+18
| | | | | - Fix typo in company name (missing 'a') - Updated SPDX license identifier to version 3.0
* mpm: mg: Move MgCPLD, TCA6408, DboardClockControl class to own moduleMartin Braun2018-02-143-195/+209
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* mpm: mg: add cpld revision to dboard infoTrung N Tran2018-02-121-5/+7
| | | | Reviewed-by: Martin Braun <martin.braun@ettus.com>
* fixup! mpm: Changed mpm_shell to support scripted useMoritz Fischer2018-02-071-26/+31
| | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* mpm: magnesium_update_cpld.py: Add axi_bitq supportMoritz Fischer2018-02-071-19/+65
| | | | | | | | | | | | Add axi_bitq support. In order for this to work we need several conditions to be true: - Updated openocd - FPGA image with axi_bitq built in and hooked up to correct pins - Updated overlays matching the FPGA image - An svf file with correct max frequency <= 10MHz Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* mpm: mg: Remove superfluous importMartin Braun2018-01-231-1/+1
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* mg: ease the usage of init and tracking calTrung N Tran2018-01-231-9/+94
| | | | | | | | Using string expression instead of passing in a total hex value. Now user can passed in for example: init_cals=DEFAULT or init_cals=BASIC|TX_QEC_INIT Reviewed-by: Martin Braun <martin.braun@ettus.com>
* n310: Update the dboard UIO usageBrent Stapleton2018-01-191-25/+22
| | | | | Updating the UIO usage in the debug functions in magnesium.py. Somehow this didn't get updated before.
* mpm: mg: Demote notice on LMK not being locked b/c of lacking initMartin Braun2018-01-181-1/+1
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* mpm: Demoted some log statements from INFO to TRACE or DEBUGMartin Braun2018-01-171-2/+1
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* mpm: mg: Pass deserializer_lane_xbar to ad937x_configTrung N Tran2018-01-121-0/+8
| | | | | | | | | Slot A and Slot B are different in how the JESD lanes are connected. We now pass in different deserializer_lane_xbar config values for each slot. Reviewed-by: Martin Braun <martin.braun@ettus.com> Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com> Reviewed-by: Mark Meserve <mark.meserve@ni.com>
* mpm: n310: Fix various bugs in sensor APIMartin Braun2018-01-121-1/+1
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* mpm: tdc: add signature/revision checks and master reset routinedjepson12018-01-121-0/+1
| | | | Reviewed-by: Martin Braun <martin.braun@ettus.com>
* mpm: dboard_manager: Use mpmutils.to_native_str instead of local hackMartin Braun2018-01-111-10/+2
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* fixup! mpm: mg: Added magnesium_update_cpld.pyBrent Stapleton2018-01-051-1/+1
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* mpm: mg: Assert that ref clock freq was actually set before init()Martin Braun2018-01-051-5/+7
| | | | | | | There was a theoretical chance otherwise that we forgot to set the ref_clock_freq value and it set up the LMK incorrectly. Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
* mg cpld: update compatibility checking to major/minordjepson12018-01-041-18/+19
| | | | | Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com> Reviewed-by: Martin Braun <martin.braun@ettus.com>
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