mpm: Fix some Pylint warnings

No functional changes.

2 files changed, 12 insertions, 11 deletions

diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
index 3cb6ea7c9..e7327ee83 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
@@ -40,13 +40,13 @@ class LMK04828Mg(LMK04828):
         self.pll2_vco_freq  = (self.vcxo_freq/self.pll2_r_divider)*self.pll2_prescaler*self.pll2_n_divider
         self.log.trace("Variable Configuration Report: "
                        "clkin1_r = 0d{}, clkout_div = 0d{}, pll1_n = 0d{}"
-           .format(self.clkin_r_divider, self.clkout_divider, self.pll1_n_divider))
+                       .format(self.clkin_r_divider, self.clkout_divider, self.pll1_n_divider))
         self.log.trace("Variable Configuration Report: "
                        "sysref_divider = 0d{}, pll2_pre = 0d{}, pll2_n = 0d{}"
-           .format(self.sysref_divider, self.pll2_prescaler, self.pll2_n_divider))
+                       .format(self.sysref_divider, self.pll2_prescaler, self.pll2_n_divider))
         self.log.trace("Variable Configuration Report: "
                        "pll2_vco_freq = 0d{}"
-           .format(self.pll2_vco_freq))
+                       .format(self.pll2_vco_freq))
         # Run .init() and .config() right off the bat. Save clock shifty-ness for later.
         self.init()
         self.config()
@@ -232,7 +232,8 @@ class LMK04828Mg(LMK04828):
         Apply time shift using the dynamic digital delays inside the LMK.
         """
         self.log.trace("Clock Shifting Commencing using Dynamic Digital Delay...")
-        ddly_value = self.divide_to_cnth_cntl_reg(self.clkout_divider+1) if num_shifts >= 0 else self.divide_to_cnth_cntl_reg(self.clkout_divider-1)
+        ddly_value = self.divide_to_cnth_cntl_reg(self.clkout_divider+1) \
+                if num_shifts >= 0 else self.divide_to_cnth_cntl_reg(self.clkout_divider-1)
         ddly_value_sysref = self.sysref_divider+1 if num_shifts >= 0 else self.sysref_divider-1
         self.pokes8((
             (0x141, 0xB1), # Dynamic digital delay enable on outputs 0, 8, 10
@@ -248,7 +249,7 @@ class LMK04828Mg(LMK04828):
             (0x13D, (ddly_value_sysref & 0x00FF) >> 0), # SYSREF DDLY value [7:0]
             (0x144, 0x4E), # Enable SYNC on outputs 0, 8, 10
         ))
-        for x in range(abs(num_shifts)):
+        for _ in range(abs(num_shifts)):
             self.poke8(0x142, 0x1)
         # Put everything back the way it was before shifting.
         self.poke8(0x144, 0xFF) # Disable SYNC on all outputs including SYSREF
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
index 7d56dea67..0eaf25ae1 100644
--- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
@@ -933,8 +933,8 @@ class Magnesium(DboardManagerBase):
     def dump_jesd_core(self):
         " Debug method to dump all JESD core regs "
         with open_uio(
-                label="dboard-regs-{}".format(self.slot_idx),
-                read_only=False
+            label="dboard-regs-{}".format(self.slot_idx),
+            read_only=False
         ) as dboard_ctrl_regs:
             for i in range(0x2000, 0x2110, 0x10):
                 print(("0x%04X " % i), end=' ')
@@ -947,8 +947,8 @@ class Magnesium(DboardManagerBase):
         Debug for accessing the DB Core registers via the RPC shell.
         """
         with open_uio(
-                label="dboard-regs-{}".format(self.slot_idx),
-                read_only=False
+            label="dboard-regs-{}".format(self.slot_idx),
+            read_only=False
         ) as dboard_ctrl_regs:
             rd_data = dboard_ctrl_regs.peek32(addr)
             self.log.trace("DB Core Register 0x{:04X} response: 0x{:08X}".format(addr, rd_data))
@@ -959,8 +959,8 @@ class Magnesium(DboardManagerBase):
         Debug for accessing the DB Core registers via the RPC shell.
         """
         with open_uio(
-                label="dboard-regs-{}".format(self.slot_idx),
-                read_only=False
+            label="dboard-regs-{}".format(self.slot_idx),
+            read_only=False
         ) as dboard_ctrl_regs:
             self.log.trace("Writing DB Core Register 0x{:04X} with 0x{:08X}...".format(addr, data))
             dboard_ctrl_regs.poke32(addr, data)