uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	mpm: tdc: add signature/revision checks and master reset routine	djepson1	2018-01-12	1	-1/+61
*	jesd: mg bug fix: default state of the RX link is scrambled	djepson1	2018-01-05	1	-1/+1
*	jesd: add in detailed error reporting for JESD204b links	djepson1	2018-01-04	1	-30/+83
*	mpm: tdc: fixed typos in comments	Daniel Jepson	2017-12-22	1	-1/+1
*	mpm: tdc: compensate for the trace delay differences between daughterboards	Daniel Jepson	2017-12-22	1	-1/+8
*	mpm: Harmonize all license header	Martin Braun	2017-12-22	4	-51/+8
*	mpm: Harmonize imports, tidy + sort modules	Martin Braun	2017-12-22	3	-1/+327
*	tdc: fix bug in pps capture reporting	Daniel Jepson	2017-12-22	1	-7/+18
*	n3xx: add support for 122.88 and 153.6 MHz sample clock rates	Martin Braun	2017-12-22	1	-14/+26
*	sync: add PDAC BIST test	djepson1	2017-12-22	1	-0/+80
*	mpm: tdc_sync: Fix number of samples, formatting issues	Martin Braun	2017-12-22	1	-7/+9
*	mpm: Replace MMCM lock and TDC PPS sleeps with poll_with_timeout	Martin Braun	2017-12-22	1	-8/+11
*	mpm: tdc_sync: Remove sleeps in offset polling	Martin Braun	2017-12-22	1	-7/+7
*	Sync: Improved range checking for offset measurements.	djepson1	2017-12-22	1	-2/+2
*	mg: Preliminary clock sync support	djepson1	2017-12-22	1	-6/+13
*	mpm: Update TDC sync code to make it generic for N dboards	Daniel Jepson	2017-12-22	1	-12/+62
*	mpmd/cores: Removed PPS disable logic from TDC routine and added comments	djepson1	2017-12-22	1	-10/+15
*	mpmd/cores: Adding TDC range check and removing clock enable/disable logic	djepson1	2017-12-22	1	-2/+10
*	mpm/tdc: Re-enable PPS after synchronization procedure is complete	Martin Braun	2017-12-22	1	-0/+1
*	mpm: Made code Python3-compatible	Martin Braun	2017-12-22	1	-0/+2
*	mpm: Remove numpy dependency	Martin Braun	2017-12-22	1	-1/+4
*	mpm: Replaced xrange with range for better Python future-proofing	Martin Braun	2017-12-22	1	-3/+3
*	mpm: Added TDC clock sync driver	Martin Braun	2017-12-22	3	-0/+345