| Commit message (Collapse) | Author | Age | Files | Lines |
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- Allows building static libraries
- For users calling find_package(UHD), provides extra options
for building apps statically linking UHD.
- Updated the init_usrp example to link UHD statically.
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This patch addresses issue #648 "B200: TX with SC12 format and MIMO".
The observed MIMO header corruption was caused by overwriting the
end of the packed 12-bit sample output buffer. The overwrite was due to
the converter call always writing out 4 complex samples even if less
than 4 samples were available. The extra samples would corrupt data with
zero padding.
Avoid the overwrite condition by only writing the minimum number of
32-bit lines necessary rather than the entire 12 byte struct.
Samples 32-bit lines
1 1
2 2
3 3
4 3
Signed-off-by: Tom Tsou <tom@tsou.cc>
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- Moved setting of tick rate before setting of PPS time
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dboard info for second mboard
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Resolve issue #666 "B200: Rx signal distortion when using SC12".
During 12-bit unpacking, OTW samples are shifted into the high order
bits of the 16-bit intermediate values. The remaining 4-bits are not
zeroed and contain bits from adjacent samples. Consequently, signal
distortion becomes noticable with spurs and other random signal
garbage when operating at low signal levels.
Signed-off-by: Tom Tsou <tom@tsou.cc>
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- Updated fpga-src submodule
- Updated version strings and images package
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- X300: FPGA compat 9
- E300: FPGA compat 5
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To reflect a reality where some USRPs don't have daughterboards,
and set_xx_bandwidth doesn't necessarily set an /IF/ bandwidth.
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- Made the methods in adf4001_ctrl virtual
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external ref selection
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Signed-off-by: Moritz Fischer <moritz@ettus.com>
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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with older Pythons
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