| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Martin Braun <martin.braun@ettus.com>
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- Creates mpm/ subdirectory
- First pass at hardware daemon/MPM
- New code for LMK04828, AD9371
- spidev integration
Contributions by:
Martin Braun <martin.braun@ettus.com>
Derek Kozel <derek.kozel@ettus.com>
Mark Meserve <mark.meserve@ni.com>
Andrej Rode <andrej.rode@ettus.com>
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This is meant for headers that don't export symbols.
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- Removed stale files (i2c_core_100, spi_core_100)
- Made more compilation condiational; disabling some devices will
disable dependencies as well so they don't get compiled in by default.
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- NUM_HALFBANDS and CIC_MAX are no longer hard coded and are now
readback regs.
- both DDC and DUC use same encoding to enable halfbands
(increment the number)
- removed hacky hack & fixed get_output_rate/get_input_rate
to include only valid rates based on NUM_HALFBANDS and CIC_MAX.
- added compatibility number readback w/ warning/error messages
- Updated images package to include new DDC/DUC (affects X-Series only)
- Updated fpga-src submodule pointer
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Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
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Thanks to FX Coudert for suggesting this fix.
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ADF5355 and ADF5356 support merged into adf535x class
Default register values moved into regmap
Reviewed-By: Martin Braun <martin.braun@ettus.com>
Reviewed-By: Ashish Chaudhari <ashish@ettus.com>
Reviewed-By: Mark Meserve <mark.meserve@ni.com>
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reduce transient at start of transmission
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Also added stubs in the default impl.
Reviewed-By: Ashish Chaudhari <ashish@ettus.com>
Reviewed-By: Derek Kozel <derek.kozel@ettus.com>
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Reviewed-By: Ashish Chaudhari <ashish@ettus.com>
Reviewed-By: Derek Kozel <derek.kozel@ettus.com>
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Adding struct that contains the data and metadata for a file that
defines a component.
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The request struct passed to send() was not fully initialized, causing
code checkers to choke. This fix doesn't affect functionality (the
values were not used for anything), but removes warnings.
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- Added comment that the XCVR2450 is incompatible with X310
- Moved more devices to legacy, clarified meaning
- Added back E1x0 manual for reference purposes, but with deprecation
warning
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Remove the redundant send/recv buffer_pools from nirio_zero_copy_impl
class as no one is using them.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Check return value of liberio_chan_set_fixed_size() since it can fail,
and bad things happen if one just proceeds.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The timeout value passed in by UHD would get multiplied by USEC,
to convert from the UHD value in seconds to the liberio value in
microseconds.
The bug manifested itself by calling liberio_dequeue_buf() with a
timeout equivalent to 100s.
Fixes ed1c64c81 ('transport: Added liberio_zero_copy transport ...')
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Alex Williams <alex.williams@ni.com>
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Remove stray tabs from liberio_zero_copy transport and clarify actual
code flow by fixing indent.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Remove multi-line log message for socket creation
- Include local addr and port in trace messages
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It's feasible that error messages are sent out during overrun handling,
which would cause a nested invocation of handle_overrun(). This adds a
lock to prevent that.
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The E1x0 series is still supported on the 3.9 LTS branch.
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Similar to b431866a5, this reduces logging in static initializer blocks.
Those are prone to hang during DLL initialization.
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- uhd::usrp::mboard_eeprom_t is now simply a map. Its commit() method
has no utility being a public API call, because the user never gets
access to the appropriate I2C object (Minor API breakage)
- The central mboard_eeprom.cpp file was broken up and put into many
smaller compilation units in every device's implementation folder.
- Renamed some of the constants (e.g. B000_* -> USRP1_*, N100_* ->
N200_*)
- Removed the N000_* EEPROM code, because, well, you know, there's no
such device
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In uhd_usrp_get_rx_stream and uhd_usrp_get_tx_stream, an error will now
be propagated into the streamer handle.
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uhd_tx_streamer_last_error and uhd_usrp_last_error use
UHD_SAFE_C and so uhd_rx_streamer_last_error should as well
in order to be consistent.
Currently using UHD_SAFE_C_SAVE_ERROR.
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The ctrl_iface class will assume that a response packet is available.
There are cases where no response packet is available, in which case
sequence numbers should not get popped from the stack prematurely.
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These APIs will be moved to a non-public API in the future and should no
longer be used in user applications.
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For invalid dboard revisions stored in the EEPROM, provide a better
error message.
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The function was directly accessing the error message cache, bypassing
locks, and thus could be faulty if being called the same time as another
UHD component would update the error string.
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Specifically, remove set_tx_dc_offset() and set_tx_iq_balance() calls
that require doubles, and were given bools.
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This adds a zero copy transport using the liberio library.
Currently supported API version for liberio is 0.3, this might
still very much break, since the library is still in development.
So far nobody uses it UHD so we might as well merge it.
Signed-off-by: Alex Williams <alex.williams@ni.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The file was missing a .cpp suffix for the dma_fifo_block_ctrl_impl
file, somehow CMake was being smart and inferring the filetype.
Be explicit.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The existence of SSSE3 intrinsic headers is not a sufficient
condition that SSSE3 support is available, which may lead to
'illegal instruction' runtime failuire on some platforms. Major
OS distributions (Ubuntu, Fedora, etc.) include x86_64
intrinsic headers, though the underlying architecture may or
may not support the instruction set.
Assuming SSE2 availability is safe as instructions are present on
all x86_64 architectures for which instrinsic headers would be
present. The same cannot be said for SSSE3.
Issue: #1761
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Implementation uses SSSE3 intructions to perform 12-bit
sample pack/unpack operations to/from standard 16 and 32
bit host values. Input/output shuffle orderings for a
single 128-bit SSE register with 16-bit integers shown
below.
16-bit interleaved I/Q
---------------------------------------
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 | Input
---------------------------------------
| 127 0 |
12-bit packed I/Q byteswapped
-----------------------
| I0 | Q0 | I1 | 0
|-----------------------|
| I1 | Q1 | I2 | Q2 | Output
|-----------------------|
| Q2 | I3 | Q3 |
|-----------------------|
| Unused | 3
-----------------------
31 0
Fixes: #1740, #966
Related: #1739
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