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* Add support for LEA-M8F GPSDO boardlea-m8f-v3.14.1.0Matthias P. Braendli2019-09-059-29/+350
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* 3.14.1.0 Releasemichael-west2019-06-283-61/+80
| | | | | | | | Updated CHANGELOG Updated Debian files Updated manifest Signed-off-by: michael-west <michael.west@ettus.com>
* TwinRX: Fix tick rateMichael West2019-06-281-1/+5
| | | | Signed-off-by: Michael West <michael.west@ettus.com>
* Device3: Fix MTU and default frame sizesMichael West2019-06-287-144/+260
| | | | | | | | | | The latest changes to the get_*x_stream() functions to calculate the MTU for the channel caused default frame size values to be ignored. This change fixes that by changing the key from "send/recv_frame_size" to "mtu" and then changing the implementations of make_transport() constrain the frame size values based on the "mtu" value as well as any device and/or transport-specific limits. Signed-off-by: Michael West <michael.west@ettus.com>
* nirio: Fix typo in nirio_zero_copyMichael West2019-06-281-1/+1
| | | | Signed-off-by: Michael West <michael.west@ettus.com>
* transport: fixed a pre-mature buffer resetmcrymble2019-06-121-2/+3
| | | | | | In the PACKET_INLINE_MESSAGE case, we need to extract the error code from the packet buffer. But the buffer was being released before that happens, resulting in garbage values for metadata.error_code.
* x310: fixed udp WSA buffer size assignment issueMatthew Crymble2019-06-121-3/+21
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* twinrx: increase rev c lo1 charge pump default valueMark Meserve2019-06-032-2/+2
| | | | - This change improves spur performance for the Rev C TwinRX daughterboard
* fixup! uhdlib: add rational approximation to math utilitiesMartin Braun2019-06-031-1/+1
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* tests: Fix mock_ctrl_iface for 32-bit MSVCMartin Braun2019-06-031-2/+2
| | | | | Widening and narrowing of bitwidths causes errors on this platform without explicit casts.
* cores: Use NSDMI consistently in ?x_dsp_core_3000.*Martin Braun2019-06-032-23/+16
| | | | | | There are edge cases where the lack of initialization of _current_freq could crash libuhd. To resolve this, we initialize all elements of those cores to sensible values using NSDMI.
* cores: Apply clang-format to ?x_dsp_core_3000.*Martin Braun2019-05-302-230/+268
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* lib: rfnoc: Apply clang-format to graph_impl.hppMartin Braun2019-05-301-35/+26
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* docs: n3xx: Add link to README for building custom filesystemsSugandha Gupta2019-05-301-37/+1
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* Prepare branch for 3.14.1.0 releaseMichael West2019-05-292-166/+539
| | | | | | | | | - Updated CHANGELOG - Updated fpga-src submodule - Updated version - Updated manifest for images Signed-off-by: Michael West <michael.west@ettus.com>
* X300: fixed get_mtu for pcieMatthew Crymble2019-05-241-1/+4
| | | | Signed-off-by: Matthew Crymble <matthew.crymble@ni.com>
* rfnoc: tick_node: Search all nodes for tick ratesMartin Braun2019-05-211-3/+5
| | | | | | | | | | | | | | | | | The tick_node was trying to find the current tick rate by only querying active blocks (i.e., blocks that were flagged active-streaming). However, this is not necessary since we require all blocks to run at the same tick rate. In theory, querying active-only ports should be fine, but due to some idiosyncrasies in our current graph code, connecting a single streamer to channel 1 (out of 0, 1) would try and get the info from the wrong port. This is not a fix to the graph code, but the change to tick_node is also appropriate and is sufficient to fix the "late packets on channel 1" issue. This issue would manifest when sending timed packats to channel 1 in a single-channel streamer. The problem is that it wouldn't be able to read the correct tick rate.
* log: Fix ANSI colour codesMartin Braun2019-05-212-7/+10
| | | | | | The colour codes used for console logging were incorrectly defined. Some colours would simply not rendered this way (e.g., red), others had the boldness flag wrong.
* adf435x: run clang-formatMark Meserve2019-05-211-146/+251
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* twinrx: set lo2 to use new low spur tuning modeMark Meserve2019-05-212-6/+3
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* adf435x: add low spur tuning modeMark Meserve2019-05-211-5/+56
| | | | | - adds a new mode to the adf435x driver which provides general spur performance improvements
* uhdlib: add rational approximation to math utilitiesMark Meserve2019-05-211-0/+75
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* twinrx: add lo charge pump propertiesMark Meserve2019-05-215-19/+116
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* adf535x: add charge pump controlMark Meserve2019-05-211-3/+55
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* adf435x: add charge pump with double parameterMark Meserve2019-05-211-0/+34
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* adf435x: enhance logging messagesMark Meserve2019-05-211-10/+13
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* mpmd: Release resources on destructionVirendra Kakade2019-05-212-4/+6
| | | | | This will clear the property tree, block registry, transport managers, and motherboard list on destruction of mpmd_impl.
* liberio: Release context holder on destruction of last liberio xportSugandha Gupta2019-05-211-3/+24
| | | | | | This will make sure that the context holder for the liberio context is destroyed when the last liberio transport is destroyed, and not on termination of the program.
* mpmd: Fix spurious reclaim call after unclaimVirendra Kakade2019-05-211-3/+6
| | | | | | | | | The reclaim task loop is asnychronous to the main thread which can result in spurious reclaim call to the device after unclaim has been called. This is especially risky if the device has already entered a non-serviceable state after unclaim e.g. idle state. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* device3: Constraint send/recv_frame_size based on down/upstream MTUSugandha Gupta2019-05-2113-6/+132
| | | | | | We need to properly contraint the send/recv_frame_size based on the minimum MTU of all the down/upstream blocks. This fixes the issue with E310 tx/rx streaming as it has smaller MTU sizes than the other usrps.
* ad9361: Fix return values for tune and set_clock_rateSugandha Gupta2019-05-212-3/+11
| | | | | | This fixes a potential mismatch between the returned frequency and clock rate and the actual value. The new function get_clock_rate is need for async call to set_clock_rate in E3xx devices
* utils: Add X300/X310 reset programNick Foster2019-05-211-0/+109
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* docs: Improved Windows-related build instructionsAbdo-Gaber2019-05-211-13/+65
| | | | | | | | | | | - In general, some comments to clarify the dependencies installation and building process for windows users. - Add a comment to the required packages for MSCV. - Provide instructions to install Python requirements. - Add the instructions of NSIS installation. - Add comments to the version match between different installers. - Clarify the instructions of building process using Cmake - Add a subsection to show how a binary UHD installer can be obtained. - Correct the URL of Doxygen.
* log: fix deadlock issue on Windows machinesAbdo-Gaber2019-05-211-3/+32
| | | | | | | In log.cpp, a deadlock can occur while popping elements from the log queue. If the queue is empty, the call does not timeout, and waits infinitely. Replacing pop_with_wait() with pop_with_timed_wait() solves this issue.
* b200: enable usage of custom bootloaderMark Meserve2019-05-214-102/+403
| | | | | - Update MB EEPROM - Add bootloader load command to fx3 util
* docs: Add mention of DPDK support to X3x0Alex Williams2019-05-212-1/+9
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* uhdlib: Add dpdk_zero_copy.hppAlex Williams2019-05-216-5/+5
| | | | | dpdk_zero_copy.hpp was referenced in multiple places using relative paths. Let's throw it in uhdlib for easy access.
* x300: Add support for DPDK transportsAlex Williams2019-05-213-7/+166
| | | | | Use dpdk_simple together with a control transport factory. Where udp_zero_copy is used, use dpdk_zero_copy if use_dpdk=1.
* transport: Make dpdk_simple subclass udp_simpleAlex Williams2019-05-212-85/+77
| | | | With the same APIs, this will make it easier to add support for X310.
* X300: add capability to flash NI-2974 FPGAThomas Vogel2019-05-211-2/+7
| | | | | | The NI-2974 has a X310 inside but reports a different "product" when polled. This prevents the image_loader from flashing a new FPGA image, this patch enables this.
* uhd-dpdk: Wait for links to come up before poking MPMAlex Williams2019-05-211-4/+12
| | | | | | | | | | Occasionally, MPM would check its links before the kernel would report link up, and it would then shave those ports off the CHDR link list prematurely. This commit adds a second of wait to allow the kernel time to respond. It also includes some additional reporting of link status, since Intel PMDs may report a misleading initial state upon bring-up.
* gpsd: fix API for 'gps_read'Michael Dickens2019-05-211-0/+4
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* Revert "RFNoC: Remove incorrect flush"Michael West2019-03-251-0/+19
| | | | | | This reverts commit c8e01d4bd5bef30ef6e6080c60bc8b4706eb1200. The commit introduced random phase offsets for TwinRX phase alignment.
* Revert b993f4f0d85eee53c1256e0381c3a173af7d5833Michael West2019-03-252-12/+8
| | | | | | Revert "cores: Update rx_frontend_gen3.v controls for 1/4-rate mixer" Commit introduced 180 degree ambiguity in TwinRX phase alignment.
* TwinRX: Fix duplicate write to N value in DDCmichael-west2019-03-251-2/+1
| | | | | | | The N value was getting written twice and the second value being written was 1, which works for all use cases except when using TwinRX. This change fixes several issues with TwinRX including streaming failing to stop cleanly and incorrect decimation.
* docs: Fix typo for dpdk-num-mbufs and add config file locationAlex Williams2019-03-201-3/+7
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* RFNoC: Remove incorrect flushMichael West2019-03-051-19/+0
| | | | | | | | | | | | Removing the flush in configure_flow_control_out(). The flush is done incorrectly because it just disables flow control and allows packets to dump onto the crossbar, which could lock it up. It is also incorrect to flush when connecting blocks. A connect should just configure the SID and flow control and let any existing data flow to the newly connected block. Flushing of a block should only be done during creation or destruction of the block. Signed-off-by: Michael West <michael.west@ettus.com>
* Revert "RFNoC: Fix flush in source_block_ctrl_base"Michael West2019-03-052-4/+21
| | | | | | This reverts commit 655b9b0f8e8f8556d434404da51aaccd124bbc3a. Signed-off-by: Michael West <michael.west@ettus.com>
* x300: Change PLL CP currents in x300_clock_ctrlmguyler-ni2019-03-051-8/+8
| | | | | - modify PLL charge pump values to improve phase coherence - affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
* x300: device args: Removed invalid 200 MHz sysref rateMartin Braun2019-03-051-1/+1
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